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1. 发明授权

US06965503B2 Electro-static discharge protection circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US06965503B2
公开(公告)日：2005-11-15
申请号：US10605441
申请日：2003-09-30
申请人： John Connor , Robert J. Gauthier, Jr. , Christopher S. Putnam , Alan L. Roberts
发明人： John Connor , Robert J. Gauthier, Jr. , Christopher S. Putnam , Alan L. Roberts
IPC分类号： H01L27/02 , H02H9/00
CPC分类号： H01L27/0285
摘要： An ESD protection circuit including the following: one or more inverters (I1, I2, I3), each of the one or more inverters having an input and an output; an RC network (11) having an output node (RCT), output node (RCT) connected with the input of at least one of said one or more inverters; a clamping device (N3) joined with the output of at least one of one or more inverters (I1, I2, I3); and a feedback device (NKP) in communication with clamping device (N3) and output node (RCT) of RC network (11). An RC network may include one or more resistors, and one or more decoupling capacitors. In one embodiment, feedback device (NKP) is an NFET and each of one or more inverters (I1, I2, I3) includes a PFET and NFET pair (P0/N0, P1/N1, P2/N2).
摘要翻译：一种ESD保护电路，包括：一个或多个反相器（I 1，I 2，I 3），一个或多个反相器中的每一个具有输入和输出; 具有输出节点（RCT）的RC网络（11），与所述一个或多个逆变器中的至少一个的输入端连接的输出节点（RCT）与一个或多个逆变器（I 1，I 2，I 3）中的至少一个的输出端连接的夹持装置（N 3）; 以及与RC网络（11）的钳位装置（N 3）和输出节点（RCT）通信的反馈装置（NKP）。 RC网络可以包括一个或多个电阻器和一个或多个去耦电容器。在一个实施例中，反馈装置（NKP）是NFET，并且一个或多个反相器（I 1，I 2，I 3）中的每一个包括PFET和NFET对（P 0 / N 0，P 1 / N 1，P 2 / N 2）。

2. 发明授权

US08637353B2 Through silicon via repair 失效
标题翻译：通过硅片修复
公开(公告)号：US08637353B2
公开(公告)日：2014-01-28
申请号：US13013378
申请日：2011-01-25
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H01L21/82
CPC分类号： H01L22/30 , H01L21/76886 , H01L21/76898 , H01L22/14 , H01L22/20 , H01L25/0657 , H01L25/50 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , Y10T29/5313 , Y10T29/532 , H01L2924/00
摘要： Methods and systems for altering the electrical resistance of a wiring path. The electrical resistance of the wiring path is compared with a target electrical resistance value. If the electrical resistance of the wiring path exceeds the target electrical resistance value, an electrical current is selectively applied to the wiring path to physically alter a portion of the wiring path. The current may be selected to alter the wiring path such that the electrical resistance drops to a value less than or equal to the target electrical resistance value.
摘要翻译：用于改变布线路径的电阻的方法和系统。将布线路径的电阻与目标电阻值进行比较。如果布线路径的电阻超过目标电阻值，则选择性地向布线路径施加电流，以物理地改变布线路径的一部分。可以选择电流来改变布线路径，使得电阻下降到小于或等于目标电阻值的值。

3. 发明授权

US08503140B2 Bi-directional back-to-back stacked SCR for high-voltage pin ESD protection, methods of manufacture and design structures 有权
标题翻译：用于高压引脚ESD保护的双向背对背堆叠SCR，制造和设计结构的方法
公开(公告)号：US08503140B2
公开(公告)日：2013-08-06
申请号：US12898013
申请日：2010-10-05
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H02H9/00
CPC分类号： H01L27/0262 , H01L29/747 , H01L29/87 , H02H9/04
摘要： Bi-directional back-to-back stacked SCRs for high-voltage pin ESD protection, methods of manufacture and design structures are provided. The device includes a symmetrical bi-directional back-to-back stacked silicon controlled rectifier (SCR). An anode of a first of the back-to-back stacked SCR is connected to an input. An anode of a second of the back-to-back stacked SCR is connected to ground. Cathodes of the first and second of the back-to-back stacked SCR are connected together. Each of the symmetrical bi-directional back-to-back SCRs include a pair of diodes directing current towards the cathodes which, upon application of a voltage, become reverse biased effectively and deactivating elements from one of the symmetrical bi-directional back-to-back SCRs while the diodes of another of the symmetrical bi-directional back-to-back SCRs direct current in the same direction as the reverse biased diodes.
摘要翻译：提供用于高压针ESD保护的双向背对背堆叠SCR，制造方法和设计结构。该器件包括对称双向背对背层叠可控硅整流器（SCR）。背对背堆叠的SCR中的第一个的阳极连接到输入。背对背堆叠的SCR的第二个的阳极连接到地面。第一个和第二个背靠背堆叠的SCR的阴极连接在一起。对称双向背靠背SCR中的每一个包括一对二极管，其引导电流朝向阴极，其在施加电压时有效地变得有效地反向偏置，并且从对称的双向后向SCR中的一个去激活元件，另一个对称双向背对背SCR的二极管在与反向偏置二极管相同的方向上直流电流，反向SCR。

4. 发明授权

US08217455B2 Semiconductor-on-insulator device structures with a body-to-substrate connection for enhanced electrostatic discharge protection, and design structures for such semiconductor-on-insulator device structures 有权
标题翻译：具有用于增强静电放电保护的体对衬底连接的绝缘体上半导体器件结构以及这种绝缘体上半导体器件结构的设计结构
公开(公告)号：US08217455B2
公开(公告)日：2012-07-10
申请号：US12102032
申请日：2008-04-14
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Christopher S. Putnam , Souvick Mitra
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Christopher S. Putnam , Souvick Mitra
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L27/0248
摘要： Semiconductor-on-insulator device structures with enhanced electrostatic discharge protection, and design structures for an integrated circuit with device structures exhibiting enhanced electrostatic discharge protection. A device is formed in a body region of a device layer of a semiconductor-on-insulator substrate, which is bounded by an inner peripheral sidewall of an annular dielectric-filled isolation structure that extends from a top surface of the device layer to the insulating layer of the semiconductor-on-insulator substrate. An annular conductive interconnect extends through the body region and the insulating layer to connect the body region with the bulk wafer of the semiconductor-on-insulator substrate. The annular conductive interconnect is disposed inside the inner peripheral sidewall of the isolation structure, which annularly encircles the body region.
摘要翻译：具有增强的静电放电保护的绝缘体上半导体器件结构以及具有增强的静电放电保护的器件结构的集成电路的设计结构。一种器件形成在绝缘体上半导体衬底的器件层的体区中，该衬底由环形电介质填充的隔离结构的内周侧壁限定，该隔离结构从器件层的顶表面延伸到绝缘体绝缘体上半导体衬底的层。环形导电互连延伸穿过主体区域和绝缘层，以将体区域与绝缘体上半导体衬底的体晶片连接。环形导电互连件设置在隔离结构的内周侧壁的内侧，环形环绕主体区域。

5. 发明授权

US08101505B2 Programmable electrical fuse 有权
标题翻译：可编程电气保险丝
公开(公告)号：US08101505B2
公开(公告)日：2012-01-24
申请号：US12135242
申请日：2008-06-09
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
IPC分类号： H01L21/479 , H01L23/52
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.
摘要翻译：本发明涉及电熔丝装置，更具体地说，涉及一种形成电熔丝装置的装置和方法，所述方法包括提供连接到第二导电层的第一导电层，所述第一和第二导电层由阻挡层具有与第一导电层的第二扩散率不同的第一扩散率。通过驱动电流通过电熔丝装置而在第一导电层中产生空隙。

6. 发明授权

US07956671B2 Circuit structure and method for programming and re-programming a low power, multiple states, electronic fuse (e-fuse) 有权
标题翻译：用于编程和重新编程低功耗，多状态的电路结构和方法，电子保险丝（e-fuse）
公开(公告)号：US07956671B2
公开(公告)日：2011-06-07
申请号：US12496002
申请日：2009-07-01
申请人： Michel J. Abou-Khalil , Tom C. Lee , Junjun Li , Robert J. Gauthier, Jr. , Christopher S. Putnam , Souvick Mitra
发明人： Michel J. Abou-Khalil , Tom C. Lee , Junjun Li , Robert J. Gauthier, Jr. , Christopher S. Putnam , Souvick Mitra
IPC分类号： H01L23/52
CPC分类号： G11C17/16 , G11C11/5692 , H01L23/5252 , H01L23/5256 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L45/085 , H01L45/1206 , H01L45/14 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment of an e-fuse programming/re-programming circuit, the e-fuse has two short high atomic diffusion resistance conductor layers positioned on opposite sides and at a same end of a long low atomic diffusion resistance conductor layer. A voltage source is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces. The formation of such opens and/or shorts can be used to achieve different programming states. Other circuit structure embodiments incorporate e-fuses with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.
摘要翻译：在电熔丝编程/重新编程电路的一个实施例中，电熔丝具有位于长低的原子扩散电阻较长的导体层的相对侧和同一端的两个短的高原子扩散电阻的导体层。电压源用于改变施加到端子的电压的极性和可选的电压大小，以便控制长导体层内电子的双向流动，从而在长导体上形成开路和/或短路层 - 短导体层接口。可以使用这种打开和/或短路的形成来实现不同的编程状态。其他电路结构实施例包括具有附加导体层和附加端子的电子保险丝，以便允许甚至更多的编程状态。还公开了相关联的电熔丝编程和重新编程方法的实施例。

7. 发明授权

US07746607B2 Substrate triggering for ESD protection in SOI 有权
标题翻译： SOI中ESD保护的衬底触发
公开(公告)号：US07746607B2
公开(公告)日：2010-06-29
申请号：US11380525
申请日：2006-04-27
申请人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H02H3/22
CPC分类号： H01L27/0266
摘要： Electrostatic discharge (ESD) protection device and process for protecting a conventional FET. The device includes at least one FET body forming a resistance, and a triggering circuit coupled to a protection FET and the resistance. The resistance raises a voltage of the at least one body, such that the protection FET is triggered at a voltage lower than the conventional FET.
摘要翻译：静电放电（ESD）保护装置和保护常规FET的工艺。该器件包括至少一个形成电阻的FET体，以及耦合到保护FET和电阻的触发电路。电阻提高至少一个体的电压，使得保护FET在比常规FET低的电压下被触发。

8. 发明授权

US07457086B2 High voltage ESD power clamp 有权
标题翻译：高压ESD电源钳
公开(公告)号：US07457086B2
公开(公告)日：2008-11-25
申请号：US11614659
申请日：2006-12-21
申请人： Kiran V. Chatty , Robert J. Gauthier, Jr. , Mahmoud A. Mousa , Mujahid Muhammad , Christopher S. Putnam
发明人： Kiran V. Chatty , Robert J. Gauthier, Jr. , Mahmoud A. Mousa , Mujahid Muhammad , Christopher S. Putnam
IPC分类号： H02H3/20 , H02H3/22 , H02H9/04
CPC分类号： H01L27/0266 , H03K17/08142
摘要： Method and device for protecting against electrostatic discharge. The method includes configuring a gate of at least one upper transistor of a transistor network connected between power rails to be biased to a prescribed value, and coupling an electrostatic discharge event to a gate of a lower transistor of the transistor network. The at least one upper and at least one lower transistors of the transistor network are respectively coupled between the power rails from a higher voltage to a lower voltage.
摘要翻译：用于防止静电放电的方法和装置。该方法包括配置连接在电源轨之间的晶体管网络的至少一个上晶体管的栅极以被偏置到规定值，以及将静电放电事件耦合到晶体管网络的下晶体管的栅极。晶体管网络的至少一个上部和至少一个下部晶体管分别从较高电压到较低电压耦合在电源轨之间。

9. 发明授权

US08891212B2 RC-triggered semiconductor controlled rectifier for ESD protection of signal pads 有权
标题翻译： RC触发半导体可控整流器用于信号焊盘的ESD保护
公开(公告)号：US08891212B2
公开(公告)日：2014-11-18
申请号：US13079946
申请日：2011-04-05
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H02H9/04 , H03K19/003 , H01L27/02
CPC分类号： H02H9/046 , H01L27/0262 , H03K19/00361 , Y10T29/49002
摘要： RC-trigger circuits for a semiconductor controlled rectifier (SCR), methods of providing electrostatic discharge (ESD) protection, and design structures for a RC-trigger circuit. The RC-trigger circuit is coupled to an input/output (I/O) signal pad by an isolation diode and is coupled to a power supply voltage by a power supply diode. Under normal operating conditions, the isolation diode is reverse biased, isolating the RC-trigger circuit from the input/output (I/O) pad, and the power supply diode is forward biased so that the RC-trigger circuit is supplied with power. The isolation diode may become forward biased during ESD events while the chip is unpowered, causing the RC-trigger circuit to trigger an SCR configured protect the signal pad from ESD into a conductive state. The power supply diode may become reverse biased during the ESD event, which isolates the power supply rail from the ESD voltage pulse.
摘要翻译：用于半导体可控整流器（SCR）的RC触发电路，提供静电放电（ESD）保护的方法以及用于RC触发电路的设计结构。 RC触发电路通过隔离二极管耦合到输入/输出（I / O）信号焊盘，并通过电源二极管耦合到电源电压。在正常工作条件下，隔离二极管反向偏置，将RC触发电路与输入/输出（I / O）焊盘隔离，电源二极管正向偏置，使RC触发电路供电。在ESD事件期间，隔离二极管可能会在芯片未上电时产生正向偏置，导致RC触发电路触发SCR配置，从而将信号焊盘从ESD保护到导通状态。在ESD事件期间，电源二极管可能会反向偏置，从而将电源轨与ESD电压脉冲隔离。

10. 发明授权

US07786535B2 Design structures for high-voltage integrated circuits 失效
标题翻译：高压集成电路的设计结构
公开(公告)号：US07786535B2
公开(公告)日：2010-08-31
申请号：US12059034
申请日：2008-03-31
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Christopher S. Putnam , Souvick Mitra
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Christopher S. Putnam , Souvick Mitra
IPC分类号： H01L29/78
CPC分类号： H01L27/1203
摘要： Design structures for high-voltage integrated circuits. The design structure, which is formed using a semiconductor-on-insulator (SOI) substrate, may include device structure with a semiconductor body positioned between first and second gate electrodes. The first and second gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the first and second gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrently with a process forming other device isolation regions.
摘要翻译：高压集成电路的设计结构。使用绝缘体上半导体（SOI）衬底形成的设计结构可以包括具有位于第一和第二栅电极之间的半导体本体的器件结构。第一和第二栅电极和半导体本体可以由SOI衬底的单晶SOI层形成。电介质层将第一和第二栅极电极与半导体本体分开。这些电介质层通过在SOI层中限定沟槽并用介电材料填充沟槽而形成，介电材料可与形成其它器件隔离区的工艺同时进行。

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