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1. 发明授权

US07006381B2 Semiconductor device having a byte-erasable EEPROM memory 有权
标题翻译：具有字节可擦除EEPROM存储器的半导体器件
公开(公告)号：US07006381B2
公开(公告)日：2006-02-28
申请号：US10497262
申请日：2002-10-24
申请人： Guido Jozef Maria Dormans , Robertus Dominicus Joseph Verhaar , Joachim Christoph Hans Garbe
发明人： Guido Jozef Maria Dormans , Robertus Dominicus Joseph Verhaar , Joachim Christoph Hans Garbe
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , G11C16/0433 , G11C16/16
摘要： The invention relates to a semiconductor device having a byte-erasable EEPROM memory comprising a matrix of rows and columns of memory cells. In order to provide a semiconductor device having a byte-erasable EEPROM which has a reduced chip size and increased density and which is suitable for low-power applications it is proposed according to the present invention that the memory cells each comprise a selection transistor having a selection gate and, arranged in series therewith, a memory transistor having a floating gate and a control gate, the selection transistor being further connected to a source line of the byte-erasable EEPROM memory, which source line is common for a plurality of memory cells, and the memory transistor being further connected to a bit line of the byte-erasable EEPROM memory, wherein the columns of memory cells are located in separate p-type wells separated by n-type wells. Preferably, high voltage switching elements are provided for dividing global control gates into local control gates for each column of bytes.
摘要翻译：本发明涉及一种具有字节可擦除EEPROM存储器的半导体器件，其包括存储器单元的行和列的矩阵。为了提供具有字节可擦除EEPROM的半导体器件，其具有减小的芯片尺寸和增加的密度，并且适用于低功率应用，根据本发明提出，存储器单元各自包括选择晶体管，其具有选择栅极，与串联布置的具有浮置栅极和控制栅极的存储晶体管，所述选择晶体管进一步连接到所述字节可擦除EEPROM存储器的源极线，所述源极线对于多个存储单元是公共的并且存储晶体管进一步连接到字节可擦除EEPROM存储器的位线，其中存储器单元的列位于由n型阱分离的单独的p型阱中。优选地，提供高压开关元件，用于将全局控制门分成用于每列字节的本地控制门。

2. 发明申请

US20110298034A1 MEMORY CELL 审中-公开
标题翻译：记忆体
公开(公告)号：US20110298034A1
公开(公告)日：2011-12-08
申请号：US13152183
申请日：2011-06-02
申请人： Johan Dick Boter , Guoqiao Tao , Guido Jozef Maria Dormans , Joachim Christoph Hans Garbe
发明人： Johan Dick Boter , Guoqiao Tao , Guido Jozef Maria Dormans , Joachim Christoph Hans Garbe
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , G11C16/3418 , H01L27/11524 , H01L29/66825 , H01L29/7881
摘要： A non-volatile memory cell (200) comprising a floating gate transistor (206) comprising a floating gate (10) positioned between a control gate (14) and a first channel region (232) and an access gate transistor (208) comprising an access gate (22) and a second channel region (234), the first channel region (232) comprising a first implant (242) with a first dosage level (234), and the second channel region comprising a second implant (244) having a second dosage level, the first dosage level being less than the second dosage level.
摘要翻译：一种包括浮置晶体管（206）的非易失性存储单元（200），其包括位于控制栅极（14）和第一沟道区域（232）之间的浮动栅极（10）和存取栅极晶体管（208）存取栅极（22）和第二沟道区域（234），所述第一沟道区域（232）包括具有第一剂量级别（234）的第一植入物（242），所述第二沟道区域包括第二植入物（244）第二剂量水平，第一剂量水平小于第二剂量水平。

3. 发明申请

US20090049548A1 Semiconductor Device and Method For Preventing Attacks on the Semiconductor Device 审中-公开
标题翻译：用于防止对半导体器件的攻击的半导体器件和方法
公开(公告)号：US20090049548A1
公开(公告)日：2009-02-19
申请号：US12090732
申请日：2006-10-16
申请人： Joachim Christoph Hans Garbe , Soenke Ostertun
发明人： Joachim Christoph Hans Garbe , Soenke Ostertun
IPC分类号： G06F21/02 , G06F12/16 , G06F12/00
CPC分类号： G06F21/554 , G06F21/77 , G06F2221/2101 , G06F2221/2137
摘要： The invention relates to a method and to a semiconductor device, comprising means for detecting an unauthorized access to the semiconductor device, wherein the semiconductor device carries out an initialization of the semiconductor device following detection of an unauthorized access, wherein an information item relating to the unauthorized access can be stored by the semiconductor device prior to the initialization, and wherein the stored information item relating to the unauthorized access remains intact following the initialization of the semiconductor device. It is advantageously provided that the stored information item remains intact for a predetermined period of time following disconnection of the semiconductor device from a power supply.
摘要翻译：本发明涉及一种方法和半导体器件，包括用于检测对半导体器件的未经授权的访问的装置，其中半导体器件在检测到未经授权的访问之后执行半导体器件的初始化，其中与在初始化之前，半导体器件可以存储未经授权的访问，并且其中与半导体器件的初始化之后的与未授权访问有关的所存储的信息项保持不变。有利的是，在将半导体器件从电源断开之后的预定时间段内，存储的信息项保持完整。

4. 发明申请

US20080256415A1 Error Detection/Correction Circuit as Well as Corresponding Method 审中-公开
标题翻译：错误检测/纠正电路以及相应的方法
公开(公告)号：US20080256415A1
公开(公告)日：2008-10-16
申请号：US12067977
申请日：2006-09-19
申请人： Soenke Ostertun , Joachim Christoph Hans Garbe
发明人： Soenke Ostertun , Joachim Christoph Hans Garbe
IPC分类号： H03M13/05 , G06F11/08
CPC分类号： G06F11/1008
摘要： In order to provide an error detection/correction circuit (100; 100′) as well as a method for detecting and/or for correcting at least one error of at least one data word, said data word comprising—information in the form of at least one information bit or at least one pay load data bit, and—redundancy in the form of at least one check bit or at least one redundant bit, wherein the number of the one or more check bits or redundant bits being supplemented to the respective data word is optimized, in particular wherein at least one physical memory space can be used in an optimized way depending on the requirements of the application, it is proposed—to perform at least one first error correction scheme being assigned to at least one first data path (30; 30′), and—to perform at least one second error correction scheme—being assigned to at least one second data path (40; 40), and—being designed for increasing the information and/or the redundancy, in particular—for increasing the number of the one or more information bits or of the one or more pay load data bits and/or—for increasing the number of the one or more check bits or of the one or more redundant bits, of the respective data word being transmitted through the second data path (40; 40).
摘要翻译：为了提供错误检测/校正电路（100; 100'）以及用于检测和/或校正至少一个数据字的至少一个错误的方法，所述数据字包括以下形式的信息：以至少一个信息位或至少一个有效负载数据位，以及至少一个校验位或至少一个冗余位形式的冗余，其中所述一个或多个校验位或冗余位的数量被补充到相应的数据字被优化，特别是其中至少一个物理存储器空间可以根据应用的要求以优化的方式使用，因此建议执行至少一个第一纠错方案被分配给至少一个第一数据路径（30; 30'），以及 - 执行被分配给至少一个第二数据路径（40; 40）的至少一个第二错误校正方案，并被设计用于增加信息和/或冗余特别是增加麻木所述一个或多个信息比特或所述一个或多个付费负载数据比特和/或用于增加正在发送的相应数据字的一个或多个校验比特或所述一个或多个冗余比特的数目第二数据路径（40; 40）。

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