专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06903959B2 Sensing of memory integrated circuits 失效
标题翻译：感应存储器集成电路
公开(公告)号：US06903959B2
公开(公告)日：2005-06-07
申请号：US10065168
申请日：2002-09-24
申请人： Thomas Roehr , Hans-Oliver Joachim , Joerg Wohlfahrt , Norbert Rehm
发明人： Thomas Roehr , Hans-Oliver Joachim , Joerg Wohlfahrt , Norbert Rehm
IPC分类号： G11C7/06 , G11C7/14 , G11C11/22
CPC分类号： G11C7/14 , G11C7/062 , G11C11/22
摘要： A memory IC having improved sensing during reads is disclosed. The IC includes the use of first and second reference voltages for sensing to compensate for asymmetry that exists between cells on bitline true and bitline complement. The first reference voltage is used for sensing a cell on bitline true while the second reference voltage is used for sensing a cell on bitline complement.
摘要翻译：公开了一种在读取期间具有改进的感测的存储器IC。 IC包括使用第一和第二参考电压进行感测以补偿存在于位线真数和位线补码之间的单元之间的不对称性。第一个参考电压用于在位线真时感测单元，而第二个参考电压用于感测位线补码上的单元。

2. 发明授权

US06999887B2 Memory cell signal window testing apparatus 失效
标题翻译：存储单元信号窗口测试仪
公开(公告)号：US06999887B2
公开(公告)日：2006-02-14
申请号：US10636369
申请日：2003-08-06
申请人： Norbert Rehm , Hans-Oliver Joachim , Michael Jacob , Joerg Wohlfahrt
发明人： Norbert Rehm , Hans-Oliver Joachim , Michael Jacob , Joerg Wohlfahrt
IPC分类号： G06F3/06
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5004
摘要： A memory cell signal window testing apparatus 101 and method for testing the signal window of a memory are disclosed. First data is written to a memory cell during a write cycle. A low cell signal is read from the memory cell during a first read cycle. A comparison is made between the low signal and a low reference signal. The result of the comparison is stored in a first storage register. Second data is then written to the memory cell during a write cycle. A high cell signal is read from the memory cell during a second read cycle. A comparison is made between the high cell signal and a high reference signal. The result of the comparison is stored in a second storage register. The results in the first and second storage registers are compared and an output is provided indicating that the memory cell has failed the test if the comparison shows that both the low cell signal is higher than the low reference signal and the high cell signal is lower than the high reference signal.
摘要翻译：公开了一种用于测试存储器的信号窗口的存储单元信号窗口测试装置101和方法。在写入周期期间，首先将数据写入存储单元。在第一读取周期期间从存储器单元读取低电平信号。比较低信号和低参考信号。比较结果存储在第一存储寄存器中。在写入周期期间，第二个数据被写入存储单元。在第二读取周期期间，从存储器单元读取高电平信号。在高电平信号和高参考信号之间进行比较。比较结果存储在第二存储寄存器中。比较第一和第二存储寄存器中的结果，并且提供指示如果比较显示低电平信号低于低参考信号并且高电平信号低于的信号，则存储器单元未通过测试的输出高参考信号。

3. 发明授权

US06826099B2 2T2C signal margin test mode using a defined charge and discharge of BL and /BL 失效
标题翻译： 2T2C信号余量测试模式使用BL和/ BL定义充放电
公开(公告)号：US06826099B2
公开(公告)日：2004-11-30
申请号：US10301529
申请日：2002-11-20
申请人： Hans-Oliver Joachim , Thomas Roehr , Joerg Wohlfahrt
发明人： Hans-Oliver Joachim , Thomas Roehr , Joerg Wohlfahrt
IPC分类号： G11C700
CPC分类号： G11C29/50 , G11C11/22
摘要： A semiconductor memory test mode configuration includes a first capacitor for storing digital data. The first capacitor connects a cell plate line to a first bit line through a first select transistor which is activated through a connection to a word line. A second capacitor for storing digital data connects the cell plate line to a second bit line through a second select transistor which is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines. A constant current mover, for example a constant current sink or source, is connected to the first bit line through a third transistor for changing the amount of charge on the first bit line when the third transistor is turned on to reduce the differential read signal.
摘要翻译：半导体存储器测试模式配置包括用于存储数字数据的第一电容器。第一电容器通过第一选择晶体管将单元板线连接到第一位线，该第一选择晶体管通过与字线的连接被激活。用于存储数字数据的第二电容器通过第二选择晶体管将单元板线连接到第二位线，第二选择晶体管也通过与字线的连接而被激活。感测放大器连接到第一和第二位线，用于测量第一和第二位线上的差分读取信号。恒定电流移动器，例如恒定电流吸收器或源极，通过第三晶体管连接到第一位线，用于当第三晶体管导通时改变第一位线上的电荷量，以减小差分读取信号。

4. 发明授权

US06885597B2 Sensing test circuit 失效
标题翻译：感应测试电路
公开(公告)号：US06885597B2
公开(公告)日：2005-04-26
申请号：US10065011
申请日：2002-09-10
申请人： Thomas Roehr , Hans-Oliver Joachim , Michael Jacob , Joerg Wohlfahrt , Takashima Daisaburo
发明人： Thomas Roehr , Hans-Oliver Joachim , Michael Jacob , Joerg Wohlfahrt , Takashima Daisaburo
IPC分类号： G11C29/50 , G11C29/00
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/1204 , G11C2029/5004
摘要： A test circuit for testing differential read signals during a memory access is disclosed. The test circuit is coupled to a pair of bit lines. During a read access, a selected memory cell produces a differential read signal on the bit lines. When the test circuit is activated, the magnitude of the differential read signal is varied. This enables easy testing of read signal margins in, for example, memory ICs.
摘要翻译：公开了一种用于在存储器访问期间测试差分读取信号的测试电路。测试电路耦合到一对位线。在读访问期间，所选存储单元在位线上产生差分读信号。当测试电路被激活时，差分读取信号的幅度是变化的。这使得能够容易地测试例如存储器IC中的读取信号余量。

5. 发明申请

US20050063212A1 Reference circuit implemented to reduce the degradation of reference capacitors providing reference voltages for 1T1C FeRAM devices 审中-公开
标题翻译：实现参考电路，以减少为1T1C FeRAM器件提供参考电压的参考电容的劣化
公开(公告)号：US20050063212A1
公开(公告)日：2005-03-24
申请号：US10665401
申请日：2003-09-18
申请人： Michael Jacob , Norbert Rehm , Hans-Oliver Joachim , Joerg Wohlfahrt
发明人： Michael Jacob , Norbert Rehm , Hans-Oliver Joachim , Joerg Wohlfahrt
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C2029/5002 , G11C2029/5004
摘要： A semiconductor memory comprises a first capacitor for storing digital data connecting a cell plate line to a first bit-line through a first select transistor. The first select transistor is activated through a connection to a word line. At least one reference capacitor provides a reference voltage to a reference bit-line. A sense amplifier connected to the first and reference bit-lines measures a differential read signal on the first and reference bit-lines. A toggle flip flop alternately changes the polarization of charge stored on the reference capacitors.
摘要翻译：半导体存储器包括用于存储通过第一选择晶体管将单元板线连接到第一位线的数字数据的第一电容器。第一个选择晶体管通过与字线的连接来激活。至少一个参考电容器为参考位线提供参考电压。连接到第一和参考位线的读出放大器测量第一和参考位线上的差分读取信号。触发触发器交替地改变存储在参考电容器上的电荷的极化。

6. 发明申请

US20050033541A1 Memory cell signal window testing apparatus 失效
标题翻译：存储单元信号窗口测试仪
公开(公告)号：US20050033541A1
公开(公告)日：2005-02-10
申请号：US10636369
申请日：2003-08-06
申请人： Norbert Rehm , Hans-Oliver Joachim , Michael Jacob , Joerg Wohlfahrt
发明人： Norbert Rehm , Hans-Oliver Joachim , Michael Jacob , Joerg Wohlfahrt
IPC分类号： G06F19/00 , G11C11/22 , G11C11/4197 , G11C16/34 , G11C29/00 , G11C29/50
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5004
摘要： A memory cell signal window testing apparatus 101 and method for testing the signal window of a memory are disclosed. First data is written to a memory cell during a write cycle. A low cell signal is read from the memory cell during a first read cycle. A comparison is made between the low signal and a low reference signal. The result of the comparison is stored in a first storage register. Second data is then written to the memory cell during a write cycle. A high cell signal is read from the memory cell during a second read cycle. A comparison is made between the high cell signal and a high reference signal. The result of the comparison is stored in a second storage register. The results in the first and second storage registers are compared and an output is provided indicating that the memory cell has failed the test if the comparison shows that both the low cell signal is higher than the low reference signal and the high cell signal is lower than the high reference signal.
摘要翻译：公开了一种用于测试存储器的信号窗口的存储单元信号窗口测试装置101和方法。在写入周期期间，首先将数据写入存储单元。在第一读取周期期间从存储器单元读取低电平信号。比较低信号和低参考信号。比较结果存储在第一存储寄存器中。在写入周期期间，第二个数据被写入存储单元。在第二读取周期期间，从存储器单元读取高电平信号。在高电平信号和高参考信号之间进行比较。比较结果存储在第二存储寄存器中。比较第一和第二存储寄存器中的结果，并且提供指示如果比较显示低电平信号低于低参考信号并且高电平信号低于的信号，则存储器单元未通过测试的输出高参考信号。

7. 发明授权

US06807084B1 FeRAM memory device 失效
标题翻译： FeRAM存储器件
公开(公告)号：US06807084B1
公开(公告)日：2004-10-19
申请号：US10418734
申请日：2003-04-17
申请人： Joerg Wohlfahrt , Hans-Oliver Joachim
发明人： Joerg Wohlfahrt , Hans-Oliver Joachim
IPC分类号： G11C1122
CPC分类号： G11C11/22 , G11C7/20
摘要： A FeRAM memory chip comprises an array 5 of non-volatile ferrocapacitor memory cells for storing data. Input pins receive data to be stored, and address data indicating where in the array of memory cells the data should be stored. The FeRAM memory chip further has a reset unit 7 for recognizing an externally applied reset signal. The reset unit 7, upon recognition of the reset signal, initiates a reset operation in which at least a portion of the data stored in the memory cells is set to predetermined values.
摘要翻译：一个FeRAM存储器芯片包括用于存储数据的非易失性二元电容器存储器单元阵列5。输入引脚接收要存储的数据，以及指示存储单元数组中应存储数据的位置的地址数据。 FeRAM存储器芯片还具有用于识别外部施加的复位信号的复位单元7。复位单元7在识别到复位信号时启动复位操作，其中存储在存储单元中的数据的至少一部分被设置为预定值。

8. 发明授权

US07003432B2 Method of and system for analyzing cells of a memory device 失效
标题翻译：用于分析存储器件单元的方法和系统
公开(公告)号：US07003432B2
公开(公告)日：2006-02-21
申请号：US10749460
申请日：2003-12-30
申请人： Joerg Wohlfahrt , Thomas Hladschik , Jens Holzhaeuser , Dieter Rathei
发明人： Joerg Wohlfahrt , Thomas Hladschik , Jens Holzhaeuser , Dieter Rathei
IPC分类号： G01R31/00 , G06F19/00
CPC分类号： G11C29/56 , G11C29/56008 , G11C2029/5604
摘要： A method of analyzing cells of a memory device is disclosed. Generally, a plurality of fail signatures is generated, wherein each fail signature is associated with a type of failure. Voltages according to a plurality of test patterns are applied to nodes of a cell of the memory device. Fail data of the cell for the plurality of patterns is then analyzed, and a fail signature of the cell is determined. A type of failure of the cell based upon the plurality of fail signatures is then determined. A system for analyzing cells of a memory device is also disclosed. The system generally includes a plurality of probes applying different voltages to a cell of the memory device. A control circuit varies the voltages applied to the cell, and compares the failures of the cell as the test voltage applied to the cell is varied to an artificial bit map. Finally, an output device generates an output indicating a type of failure of the cell.
摘要翻译：公开了一种分析存储器件的单元的方法。通常，生成多个故障签名，其中每个故障签名与一种故障相关联。根据多个测试图案的电压被施加到存储器件的单元的节点。然后分析多个模式的单元的失败数据，并且确定单元的失败签名。然后确定基于多个失败签名的小区的一种故障。还公开了一种用于分析存储器件单元的系统。该系统通常包括向存储器件的单元施加不同电压的多个探针。控制电路改变施加到单元的电压，并且当施加到单元的测试电压变化到人造位图时，比较单元的故障。最后，输出设备生成指示单元故障类型的输出。

9. 发明授权

US06720598B1 Series memory architecture 失效
标题翻译：系列内存架构
公开(公告)号：US06720598B1
公开(公告)日：2004-04-13
申请号：US10065124
申请日：2002-09-19
申请人： Joerg Wohlfahrt
发明人： Joerg Wohlfahrt
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , H01L27/11507
摘要： An IC with a memory array having a series architecture is disclosed. The memory cells of the series group are arranged in pairs in which the capacitors of a memory cell pair are stacked one on top of the other. This advantageously allows for larger capacitor arrays without increasing the chip size.
摘要翻译：公开了具有串联结构的存储器阵列的IC。串联组的存储单元成对布置，其中存储单元对的电容器一个堆叠在一起。这有利地允许更大的电容器阵列而不增加芯片尺寸。

10. 发明授权

US06639824B1 Memory architecture 有权
标题翻译：内存架构
公开(公告)号：US06639824B1
公开(公告)日：2003-10-28
申请号：US10065126
申请日：2002-09-19
申请人： Joerg Wohlfahrt , Norbert Rehm , Michael Jacob , Thomas Roehr
发明人： Joerg Wohlfahrt , Norbert Rehm , Michael Jacob , Thomas Roehr
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： An IC with memory cells arranged in groups is described. The memory cells, for example, are ferroelectric memory cells. The IC includes a variable voltage generator (VVG) for generating an output voltage having a different voltage level depending on a location of an addressed memory cell within the memory group is provided. By providing different voltage levels for reads and/or writes, signal loss caused by capacitances which is dependent on the location of the memory cell within the group can be avoided. This improves read and/or write operations in series memory architectures.
摘要翻译：描述了具有分组排列的存储单元的IC。存储单元例如是铁电存储单元。该IC包括一个可变电压发生器（VVG），用于根据存储器组内寻址的存储器单元的位置产生具有不同电压电平的输出电压。通过为读取和/或写入提供不同的电压电平，可以避免由取决于组内的存储器单元的位置的电容引起的信号损失。这改善了串行存储器架构中的读取和/或写入操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式