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1. 发明授权

US06535395B2 Processor power delivery system 有权
公开(公告)号：US06535395B2
公开(公告)日：2003-03-18
申请号：US10005464
申请日：2001-12-03
申请人： Joe A. Harrison , Edward R. Stanford , Thomas G. Ruttan
发明人： Joe A. Harrison , Edward R. Stanford , Thomas G. Ruttan
IPC分类号： H01R1222
CPC分类号： H05K1/141 , G06F1/189 , H05K1/0263 , H05K3/325 , H05K3/368 , H05K7/1092 , H05K2201/045 , H05K2201/049 , H05K2201/09345 , H05K2201/10325 , H05K2201/10378 , H05K2201/10734 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144
摘要： A system for delivering power to a processor enables a DC-to-DC converter substrate to be secured to the processor carrier in the Z-axis direction. The ability to assemble the converter to the processor in this way facilitates assembly compared to systems in which the converter is plugged in to the processor carrier in the direction substantially parallel to the surface of the motherboard.

2. 发明授权

US06360431B1 Processor power delivery system 失效
公开(公告)号：US06360431B1
公开(公告)日：2002-03-26
申请号：US09853279
申请日：2001-05-11
申请人： Joe A. Harrison , Edward R. Stanford , Thomas G. Ruttan
发明人： Joe A. Harrison , Edward R. Stanford , Thomas G. Ruttan
IPC分类号： H05K330
CPC分类号： H05K1/141 , G06F1/189 , H05K1/0263 , H05K3/325 , H05K3/368 , H05K7/1092 , H05K2201/045 , H05K2201/049 , H05K2201/09345 , H05K2201/10325 , H05K2201/10378 , H05K2201/10734 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144
摘要： A system for delivering power to a processor enables a DC-to-DC converter substrate to be secured to the processor carrier in the Z-axis direction. The ability to assemble the converter to the processor in this way facilitates assembly compared to systems in which the converter is plugged in to the processor carrier in the direction substantially parallel to the surface of the motherboard.

3. 发明授权

US06523253B1 Z-axis processor power delivery system 有权
标题翻译： Z轴处理器供电系统
公开(公告)号：US06523253B1
公开(公告)日：2003-02-25
申请号：US09583927
申请日：2000-05-31
申请人： Joe A. Harrison , Edward R. Stanford
发明人： Joe A. Harrison , Edward R. Stanford
IPC分类号： H05K330
CPC分类号： G06F1/189 , G06F1/183 , H05K1/0263 , H05K1/141 , H05K3/325 , H05K3/368 , H05K2201/045 , H05K2201/10325 , H05K2201/10734 , H05K2203/167 , Y10T29/4913 , Y10T29/49133 , Y10T29/49137 , Y10T29/49169
摘要： A system for delivering power to a processor enables a DC-to-DC converter substrate to be secured to the processor carrier in the Z-axis direction. The ability to assemble the converter to the processor in this way facilitates assembly compared to systems in which the converter is plugged in to the processor carrier in the direction substantially parallel to the surface of the motherboard.
摘要翻译：用于向处理器传送电力的系统使得DC-DC转换器基板能够在Z轴方向上固定到处理器载体。与转换器以大致平行于母板表面的方向插入处理器载体的系统相比，以这种方式将转换器组装到处理器的能力便于组装。

4. 发明授权

US06930889B2 Circuit board and slot connector assembly 失效
标题翻译：电路板和插槽连接器组件
公开(公告)号：US06930889B2
公开(公告)日：2005-08-16
申请号：US09811063
申请日：2001-03-16
申请人： Joe A. Harrison , Edward R. Stanford , Daniel S. Kingsley , Kelli A. Wise
发明人： Joe A. Harrison , Edward R. Stanford , Daniel S. Kingsley , Kelli A. Wise
IPC分类号： H01R12/70 , H01R12/72 , H05K1/11 , H01R9/00
CPC分类号： H01R12/721 , H01R12/7005 , H05K1/117 , H05K2201/094 , H05K2201/10189
摘要： A circuit board includes a substrate and electrical contacts to mate with a slot connector. The contacts include a first set of contacts that are associated with the communication of power and second set of contacts that are associated with the communication of signals and are not used to communicate power. Adjacent contacts of the first set have a first spacing, and adjacent contacts of the second set have a second spacing different from the first spacing. The circuit board has a retention profile to engage a retention mechanism of the slot connector. A housing of the slot connector may be made from a material that has a thermal conductivity of at least 0.27 W/m·K, and the slot connector housing may include fins that are formed on the slot connector to conduct heat away from circuitry of the circuit board.
摘要翻译：电路板包括基板和与插槽连接器配合的电触头。触点包括与电力通信相关联的第一组触点和与信号通信相关联并且不用于传达电力的第二组触点。第一组的相邻触点具有第一间隔，并且第二组的相邻触点具有与第一间隔不同的第二间隔。电路板具有保持轮廓以接合槽连接器的保持机构。槽连接器的壳体可以由具有至少0.27W / mK的热导率的材料制成，并且槽连接器壳体可以包括形成在槽连接器上以将热量从电路板的电路传导出来的散热片。

5. 发明授权

US09606595B2 Microprocessor-assisted auto-calibration of voltage regulators 有权
公开(公告)号：US09606595B2
公开(公告)日：2017-03-28
申请号：US13994065
申请日：2011-12-30
申请人： Ankush Varma , Jeremy J. Shrall , Krishnakanth Venkata Sistla , Avinash N. Ananthakrishnan , Vivek Garg , Christopher A. Poirier, Sr. , Martin T. Rowland , Edward R. Stanford
发明人： Ankush Varma , Jeremy J. Shrall , Krishnakanth Venkata Sistla , Avinash N. Ananthakrishnan , Vivek Garg , Christopher A. Poirier, Sr. , Martin T. Rowland , Edward R. Stanford
IPC分类号： G06F1/26 , G06F1/32 , G06F11/30
CPC分类号： G06F1/26 , G06F1/32 , G06F1/3206 , G06F1/3293 , G06F1/3296 , G06F11/3024 , G06F11/3058
摘要： Dynamic runtime calibration of a processor with respect to a specific voltage regulator that powers the processor or a memory subsystem coupled to the processor can reduce or eliminate the need for guardbands in power management computations. The processor receives a current measurement from the voltage regulator and computes a calibration factor based on the measured value and a stored expected value. The calibration factor can be used in making power management decisions instead of adding the guardband to power readings. A manufacturer or distributor of the processor can compute the stored values with a controlled voltage supply that has a higher precision than typical commercial power supplies used in computing systems. The computed, stored values indicate the expected value, which can be used to determine a calibration factor relative to a voltage regulator of an active system.

6. 发明申请

US20110199153A1 Simultaneous Multi-Voltage Rail Voltage Regulation Messages 有权
标题翻译：同步多电压电压调节信息
公开(公告)号：US20110199153A1
公开(公告)日：2011-08-18
申请号：US13094599
申请日：2011-04-26
申请人： Hung-Piao Ma , Alon Naveh , Gil Schwarzband , Annabelle Pratt , Jorge Pedro Rodriguez , Joseph T. Dibene, II , Sean M. Welch , Kosta Luria , Edward R. Stanford
发明人： Hung-Piao Ma , Alon Naveh , Gil Schwarzband , Annabelle Pratt , Jorge Pedro Rodriguez , Joseph T. Dibene, II , Sean M. Welch , Kosta Luria , Edward R. Stanford
IPC分类号： G05F3/02
CPC分类号： H02J1/10 , G11C5/147 , H02J2001/008 , Y10T307/305 , Y10T307/658 , Y10T307/675
摘要： Methods and mechanisms to simultaneously regulate two or more supply voltages provided to an integrated circuit by a voltage regulator. In an embodiment of the invention, a voltage regulation message exchanged between the integrated circuit and the voltage regulator includes an identifier indicating two or more supply voltages selected from a plurality of supply voltages provided to the integrated circuit by the voltage regulator, where the voltage regulation message relates to the indicated two or more supply voltages. In another embodiment, the voltage regulation message indicates a desired supply voltage level to which the indicated two or more supply voltages are to transition.
摘要翻译：同时调节通过电压调节器提供给集成电路的两个或多个电源电压的方法和机制。在本发明的一个实施例中，在集成电路和电压调节器之间交换的电压调节消息包括一个标识符，该标识符指示通过电压调节器从提供给集成电路的多个电源电压中选择的两个或多个电源电压，其中电压调节消息涉及所指示的两个或更多个电源电压。在另一个实施例中，电压调节消息指示所指示的两个或更多个电源电压要转换到的期望电源电压电平。

7. 发明申请

US20110154075A1 DATA NEGOTIATION USING SERIAL VOLTAGE IDENTIFICATION COMMUNICATION 有权
标题翻译：使用串行电压鉴定通信的数据协商
公开(公告)号：US20110154075A1
公开(公告)日：2011-06-23
申请号：US12912924
申请日：2010-10-27
申请人： Waseem S. Kraipak , Jayesh Iyer , Edward R. Stanford
发明人： Waseem S. Kraipak , Jayesh Iyer , Edward R. Stanford
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F13/4291
摘要： According to some embodiments, a method and system are provided to initiate communication at an integrated circuit that is electrically coupled to a plurality of voltage regulators, determine a slowest one of the plurality of voltage regulators that is electrically coupled to the processor, transmit address information to the plurality of voltage regulators that are electrically coupled to the processor at a first speed associated with the slowest one of the plurality of voltage regulators, determine a second speed associated with a voltage regulator to which the address information is associated, and transmit a second portion of the packet at the second speed associated with the voltage regulator to which the address information is associated.
摘要翻译：根据一些实施例，提供了一种方法和系统以在集成电路中启动通信，该集成电路电耦合到多个稳压器，确定电耦合到处理器的多个电压调节器中最慢的电压调节器，发送地址信息以与所述多个电压调节器中最慢速度相关联的第一速度电耦合到所述处理器的所述多个电压调节器确定与所述地址信息相关联的电压调节器相关联的第二速度，并且发送第二以与地址信息相关联的电压调节器相关联的第二速度的分组的部分。

8. 发明授权

US07932639B2 Simultaneous multi-voltage rail voltage regulation messages 有权
标题翻译：同时多电压轨电压调节信号
公开(公告)号：US07932639B2
公开(公告)日：2011-04-26
申请号：US11968056
申请日：2007-12-31
申请人： Hung-Piao Ma , Alon Naveh , Gil Schwarzband , Annabelle Pratt , Jorge Pedro Rodriguez , Joseph T. Dibene, II , Sean M. Welch , Kosta Luria , Edward R. Stanford
发明人： Hung-Piao Ma , Alon Naveh , Gil Schwarzband , Annabelle Pratt , Jorge Pedro Rodriguez , Joseph T. Dibene, II , Sean M. Welch , Kosta Luria , Edward R. Stanford
IPC分类号： H02J1/00
CPC分类号： H02J1/10 , G11C5/147 , H02J2001/008 , Y10T307/305 , Y10T307/658 , Y10T307/675
摘要： Methods and mechanisms to simultaneously regulate two or more supply voltages provided to an integrated circuit by a voltage regulator. In an embodiment of the invention, a voltage regulation message exchanged between the integrated circuit and the voltage regulator includes an identifier indicating two or more supply voltages selected from a plurality of supply voltages provided to the integrated circuit by the voltage regulator, where the voltage regulation message relates to the indicated two or more supply voltages. In another embodiment, the voltage regulation message indicates a desired supply voltage level to which the indicated two or more supply voltages are to transition.
摘要翻译：同时调节通过电压调节器提供给集成电路的两个或多个电源电压的方法和机制。在本发明的一个实施例中，在集成电路和电压调节器之间交换的电压调节消息包括一个标识符，该标识符指示通过电压调节器从提供给集成电路的多个电源电压中选择的两个或多个电源电压，其中电压调节消息涉及所指示的两个或更多个电源电压。在另一个实施例中，电压调节消息指示所指示的两个或更多个电源电压要转换到的期望电源电压电平。

9. 发明授权

US07804733B2 System and method for memory phase shedding 有权
标题翻译：内存相位脱落的系统和方法
公开(公告)号：US07804733B2
公开(公告)日：2010-09-28
申请号：US11968142
申请日：2007-12-31
申请人： James W. Alexander , Edward R. Stanford , Devadatta V. Bodas , Howard David , Son H. Lam
发明人： James W. Alexander , Edward R. Stanford , Devadatta V. Bodas , Howard David , Son H. Lam
IPC分类号： G11C7/00
CPC分类号： G06F1/26 , G06F1/3225
摘要： Embodiments of the invention supply power to DRAM or other memory devices with a multi-phase voltage regulator. A power controller coupled to the multi-phase voltage regulator causes one or more phases of the multi-phase voltage regulator to be activated or deactivated (shed) according to predetermined criteria. Embodiments of the invention thus improve power management by providing one or more reduced power states for the memory devices. Other embodiments are described.
摘要翻译：本发明的实施例用多相电压调节器向DRAM或其他存储器件供电。耦合到多相电压调节器的功率控制器根据预定标准使多相电压调节器的一个或多个相位被激活或去激活（脱落）。因此，本发明的实施例通过为存储器件提供一个或多个降低的功率状态来改善功率管理。描述其他实施例。

10. 发明授权

US5821641A Secondary supply power referenced interlock circuit 失效
标题翻译：二次供电参考互锁电路
公开(公告)号：US5821641A
公开(公告)日：1998-10-13
申请号：US690640
申请日：1996-07-30
申请人： Frank J. Demo , Edward R. Stanford
发明人： Frank J. Demo , Edward R. Stanford
IPC分类号： G06F1/26 , H01H35/00
CPC分类号： G06F1/26 , Y10T307/826 , Y10T307/832 , Y10T307/937 , Y10T307/944
摘要： A device for enabling and disabling the supply of power from a power source to a computer, the power source having a primary side and a secondary side, the device including an interlock switch connected to the computer, the interlock switch selectably positionable between open and closed positions; and two optocouplers coupled in parallel, both of which are referenced to the secondary side of the power source. When the interlock switch is closed, the first optocoupler is active. This enables the supply of power from the power source to the computer. When the interlock switch opens, the first optocoupler shuts off. This disables the supply of power from the power source to the computer. Further when the interlock switch is opened, the second optocoupler is saturated. This overrides the regulation feedback circuitry from regulating the power supplied by the power source driving the power outputted to the computer to zero. When the interlock switch is closed, the second optocoupler operates in the linear region. This enables the regulation feedback circuitry to regulate the power supplied by the power source to the computer.
摘要翻译：一种用于启用和禁用从电源向计算机供电的装置，所述电源具有初级侧和次级侧，所述装置包括连接到所述计算机的互锁开关，所述联锁开关可选择地定位在打开和关闭之间职位; 并联并联的两个光耦合器，它们均以电源的次级侧为参考。当互锁开关闭合时，第一个光耦合器处于活动状态。这使得能够从电源向计算机供电。当互锁开关打开时，第一个光耦合器关闭。这将禁止从电源向计算机供电。此外，当互锁开关打开时，第二个光耦合器饱和。这将覆盖调节反馈电路，以调节由驱动输出到计算机的电力为零的电源提供的功率。当互锁开关闭合时，第二个光耦合器在线性区域中运行。这使得调节反馈电路能够调节由电源向计算机提供的功率。

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