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1. 发明授权

US08107151B1 Plasmonic logic device 有权
标题翻译：等离子体逻辑器件
公开(公告)号：US08107151B1
公开(公告)日：2012-01-31
申请号：US12849198
申请日：2010-08-03
申请人： Joanna N. Ptasinski , Stephen Russell
发明人： Joanna N. Ptasinski , Stephen Russell
IPC分类号： G02F1/03 , G02F1/29 , G02F1/00
CPC分类号： G02F3/00 , G02F1/0553 , G02F2203/10 , Y10S359/90
摘要： A plasmonic logic device can include a dielectric substrate, and first and second metallic input strips that are placed on the substrate. The input metallic strips can be made of different metals that support propagation of surface plasmons at different frequencies. The input metallic strips can be separated by a predetermined gap that causes for the surface plasmons to constructively combine or destructively cancel each other, according to the gap distances and strip materials chosen, to accomplish the desired logic function. A metallic output strip can be placed on the substrate at a distance from the metallic input strips that allows for selective propagation to accomplish different logic functions. The metallic output strip can further be chosen from a material that allows for propagation of surface plasmons over a broad frequency range to allow for evanescent coupling of a surface plasmon from the metallic input strips.
摘要翻译：等离子体激元逻辑器件可以包括电介质衬底以及放置在衬底上的第一和第二金属输入条。输入金属条可以由支持不同频率的表面等离子体激元传播的不同金属制成。输入金属条可以按照预定的间隙分开，这些间隙使得表面等离子体激元根据所选择的间隙距离和条带材料构造地组合或相消地相互抵消，以实现期望的逻辑功能。金属输出条可以放置在离金属输入条一定距离的基板上，允许选择性传播来完成不同的逻辑功能。金属输出条可以进一步选自允许表面等离子体激元在宽的频率范围内传播的材料，以允许表面等离子体激元与金属输入条的渐逝耦合。

2. 发明授权

US08094317B1 Plasmonic router 有权
标题翻译：等离子体路由器
公开(公告)号：US08094317B1
公开(公告)日：2012-01-10
申请号：US12793271
申请日：2010-06-03
申请人： Joanna N. Ptasinski , Stephen Russell
发明人： Joanna N. Ptasinski , Stephen Russell
IPC分类号： G01N21/55
CPC分类号： G02B6/1226 , B82Y10/00 , B82Y20/00 , G02F1/3137 , G02F2203/10
摘要： A plasmonic router can include a first surface plasmon guide and a second surface plasmon guide. A surface plasmon can be generated in either of the plasmon guides. Each plasmon guide has an energy barrier, which can be selectively decreased to allow selective propagation of the generated surface plasmon through the plasmon guide. The generated surface plasmon has an evanescent wave that extends outwardly from the plasmon guide by a spatial extent. To allow for surface plasmon propagation between plasmon guides, the plasmon guides can be spaced apart by a predetermined gap that is less than the spatial extent of the surface plasmon. When that occurs, the surface plasmon will “jump” the predetermined gap and propagate from one plasmon guide to the other plasmon guide.
摘要翻译：等离子体激元路由器可以包括第一表面等离子体引导件和第二表面等离子体引导件。可以在等离子体激元导向器中的任何一个中产生表面等离子体激元。每个等离子体引导件具有能量势垒，其可以选择性地降低，以允许所生成的表面等离子体激元选择性地传播通过等离子体激元引导。所产生的表面等离子体激元具有从等离子体引导件向外延伸空间范围的ev逝波。为了允许等离子体激元引导之间的表面等离子体激元传播，等离子体激元引导件可以间隔开小于表面等离子体的空间范围的预定间隙。当发生这种情况时，表面等离子体激元将“跳过”预定的间隙并从一个等离子体激元导向器传播到另一个等离子体引导件。

3. 发明授权

US07459324B1 Metal nanoparticle photonic bandgap device in SOI method 有权
标题翻译： SOI方法中的金属纳米粒子光子带隙器件
公开(公告)号：US07459324B1
公开(公告)日：2008-12-02
申请号：US11844192
申请日：2007-08-23
申请人： Joanna N. Ptasinski , John Scott Rodgers , Stephen Russell
发明人： Joanna N. Ptasinski , John Scott Rodgers , Stephen Russell
IPC分类号： H01L21/20
CPC分类号： G02B6/1225 , B82Y20/00 , G02B2006/12061 , Y10S977/773
摘要： A Metal Nanoparticle Photonic Bandgap Device in SOI Method (NC#098884). The method includes providing a substrate having a semiconductor layer over an insulator layer, operatively coupling the substrate to a photonic bandgap structure having at least one period, wherein the photonic bandgap structure is adapted to receive and output light along a predetermined path, and operatively coupling the photonic bandgap structure and the substrate to a metal nanoparticle structure comprising at least three metal nanoparticles having spherical shapes of different radii, wherein the at least three metal nanoparticles are adapted to receive and amplify light rays and output amplified light.
摘要翻译： SOI方法中的金属纳米粒子光子带隙器件（NC＃098884）。该方法包括提供在绝缘体层上方具有半导体层的衬底，可操作地将衬底耦合到具有至少一个周期的光子带隙结构，其中光子带隙结构适于沿着预定路径接收和输出光，以及可操作耦合所述光子带隙结构和所述衬底至金属纳米颗粒结构，其包括具有不同半径的球形形状的至少三种金属纳米颗粒，其中所述至少三种金属纳米颗粒适于接收和放大光线并输出放大的光。

4. 发明授权

US08012674B2 Efficient pitch multiplication process 有权
标题翻译：高效的音调乘法过程
公开(公告)号：US08012674B2
公开(公告)日：2011-09-06
申请号：US12687005
申请日：2010-01-13
申请人： Mark Fischer , Stephen Russell , H. Montgomery Manning
发明人： Mark Fischer , Stephen Russell , H. Montgomery Manning
IPC分类号： G03F7/26
CPC分类号： H01L29/06 , H01L21/0338 , H01L21/3088
摘要： Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.
摘要翻译：通过通过掩模处理衬底来形成集成电路的间距倍增和非间距倍数特征，例如集成电路的阵列，接口和外围区域中的特征。通过图案化光刻胶层来形成掩模，该光致抗蚀剂层同时限定对应于集成电路的阵列，界面和外围区域中的特征的掩模元件。将图案转移到无定形碳层。侧壁间隔物形成在图案化无定形碳层的侧壁上。沉积一层保护材料，然后将其图案化以暴露阵列区域中的掩模元件和界面或外围区域的选定部分。除去阵列区域或其它暴露部分中的无定形碳，从而在阵列区域中留下包括独立的，间距倍增的间隔物的图案。去除保护材料，在阵列区域中留下间距倍数间隔物的图案，并在界面和外围区域留下非间距倍增的掩模元件。将图案转移到硬掩模层，通过该硬掩模层蚀刻下面的基底。

5. 发明申请

US20110114555A1 FILTRATION MEDIA 审中-公开
标题翻译：过滤介质
公开(公告)号：US20110114555A1
公开(公告)日：2011-05-19
申请号：US12995704
申请日：2009-06-01
申请人： Stephen Coulson , Stephen Russell , Matthew Tipper
发明人： Stephen Coulson , Stephen Russell , Matthew Tipper
IPC分类号： B01D39/16 , C08J7/18
CPC分类号： B01D39/1623 , B01D39/2055 , B01D2239/0478
摘要： A fibrous filtration media such as an electrostatic filtration media, whose fibre surfaces have been modified by exposure to a plasma deposition process so as to deposit a polymeric coating thereon.
摘要翻译：一种纤维过滤介质，例如静电过滤介质，其纤维表面已通过暴露于等离子体沉积工艺进行改性，以便在其上沉积聚合物涂层。

6. 发明申请

US20100220906A1 METHODS AND SYSTEMS FOR DETERMINING OPTIMAL FEATURES FOR CLASSIFYING PATTERNS OR OBJECTS IN IMAGES 有权
标题翻译：用于确定图像中分类图案或对象的最佳特征的方法和系统
公开(公告)号：US20100220906A1
公开(公告)日：2010-09-02
申请号：US12601784
申请日：2008-05-29
申请人： Michael Abramoff , Pete Soliz , Stephen Russell
发明人： Michael Abramoff , Pete Soliz , Stephen Russell
IPC分类号： G06K9/46 , G06K9/00
CPC分类号： G06K9/66 , G06K9/6231 , G06K9/6277 , G06T7/0014
摘要： Provided are methods for determining optimal features for classifying patterns or objects. Also provided are methods for image analysis. Further provided are methods for image searching.
摘要翻译：提供了用于确定用于对图案或对象进行分类的最佳特征的方法。还提供了图像分析的方法。进一步提供图像搜索的方法。

7. 发明授权

US07666578B2 Efficient pitch multiplication process 有权
标题翻译：高效的音调乘法过程
公开(公告)号：US07666578B2
公开(公告)日：2010-02-23
申请号：US11521851
申请日：2006-09-14
申请人： Mark Fischer , Stephen Russell , H. Montgomery Manning
发明人： Mark Fischer , Stephen Russell , H. Montgomery Manning
IPC分类号： G03F7/26 , G03F7/00
CPC分类号： H01L29/06 , H01L21/0338 , H01L21/3088
摘要： Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.
摘要翻译：通过通过掩模处理衬底来形成集成电路的间距倍增和非间距倍数特征，例如集成电路的阵列，接口和外围区域中的特征。通过图案化光刻胶层来形成掩模，该光致抗蚀剂层同时限定对应于集成电路的阵列，界面和外围区域中的特征的掩模元件。将图案转移到无定形碳层。侧壁间隔物形成在图案化无定形碳层的侧壁上。沉积一层保护材料，然后将其图案化以暴露阵列区域中的掩模元件和界面或外围区域的选定部分。除去阵列区域或其它暴露部分中的无定形碳，从而在阵列区域中留下包括独立的，间距倍增的间隔物的图案。去除保护材料，在阵列区域中留下间距倍数间隔物的图案，并在界面和外围区域留下非间距倍增的掩模元件。将图案转移到硬掩模层，通过该硬掩模层蚀刻下面的基底。

8. 发明申请

US20070227465A1 Reprogrammable receiver collar 有权
标题翻译：可编程接收器轴环
公开(公告)号：US20070227465A1
公开(公告)日：2007-10-04
申请号：US11397164
申请日：2006-04-04
申请人： Duane Gerig , Stephen Russell , Paul McAfee
发明人： Duane Gerig , Stephen Russell , Paul McAfee
IPC分类号： A62B35/00
CPC分类号： A01K15/021
摘要： An animal training system including a programming apparatus and an animal training collar. The animal training collar is communicatively couplable to the programming apparatus. The animal training collar includes at least one stimulation probe and a programmable device operatively connected to the at least one stimulation probe to activate the at least one stimulation probe. The at least one stimulation probe also transferring data at least one of to and from the programming apparatus.
摘要翻译：一种动物训练系统，包括编程设备和动物训练项圈。动物训练项圈可与编程设备进行通讯连接。动物训练衣领包括至少一个刺激探针和可操作地连接到所述至少一个刺激探针以激活所述至少一个刺激探针的可编程装置。所述至少一个刺激探头还将数据传送到编程设备和从编程设备传送数据。

9. 发明授权

US06641205B1 Vehicle door sealing assembly 失效
标题翻译：车门密封总成
公开(公告)号：US06641205B1
公开(公告)日：2003-11-04
申请号：US10278681
申请日：2002-10-23
申请人： Stephen Russell , John Collins , Kazuo Onodera , Tony Kmeid
发明人： Stephen Russell , John Collins , Kazuo Onodera , Tony Kmeid
IPC分类号： B60J504
CPC分类号： B60J5/0479 , B60J10/80
摘要： An assembly for sealing a front door and a rear door in a door opening on a vehicle lacking a conventional, separate B-pillar. The front door carries an adaptor at a lower rear end thereof that defines a generally sharp corner over which a portion of the front door seal extends. The rear door defines a sealing surface that is engaged by the portion of the front door seal extending over the adaptor. The rear door includes a rear door seal, a portion of which extends over an outer surface of the rear door and is engaged a sealing surface provided by the front door. At least a portion of the rear door seal and sealing surface are integrally formed by a sealing boot disposed over a lower end of the rear door so as to create a seal-to-seal type engagement between the front and rear doors.
摘要翻译：一种用于密封前车门和后车门的组件，该组件用于没有传统的分开的B柱的车辆上的门开口中。前门在其后端承载适配器，该适配器限定了前门密封件的一部分延伸穿过的大致尖角。后门限定了一个密封表面，该密封表面由延伸在适配器上的前门密封件的部分接合。后门包括后门密封件，其一部分在后门的外表面上延伸并与由前门提供的密封表面接合。后门密封和密封表面的至少一部分由设置在后门的下端上的密封靴一体地形成，以便在前门和后门之间形成密封 - 密封型接合。

10. 发明授权

US08450829B2 Efficient pitch multiplication process 有权
标题翻译：高效的音调乘法过程
公开(公告)号：US08450829B2
公开(公告)日：2013-05-28
申请号：US13198581
申请日：2011-08-04
申请人： Mark Fischer , Stephen Russell , H. Montgomery Manning
发明人： Mark Fischer , Stephen Russell , H. Montgomery Manning
IPC分类号： H01L21/70
CPC分类号： H01L29/06 , H01L21/0338 , H01L21/3088
摘要： Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.
摘要翻译：通过通过掩模处理衬底来形成集成电路的间距倍增和非间距倍数特征，例如集成电路的阵列，接口和外围区域中的特征。通过图案化光刻胶层来形成掩模，该光致抗蚀剂层同时限定对应于集成电路的阵列，界面和外围区域中的特征的掩模元件。将图案转移到无定形碳层。侧壁间隔物形成在图案化无定形碳层的侧壁上。沉积一层保护材料，然后将其图案化以暴露阵列区域中的掩模元件和界面或外围区域的选定部分。除去阵列区域或其它暴露部分中的无定形碳，从而在阵列区域中留下包括独立的，间距倍增的间隔物的图案。去除保护材料，在阵列区域中留下间距倍数间隔物的图案，并在界面和外围区域留下非间距倍增的掩模元件。将图案转移到硬掩模层，通过该硬掩模层蚀刻下面的基底。

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