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1. 发明授权

US09780113B2 Method for fabricating semiconductor device including a first ILD with sloped surface on a stacked structure and a second ILD on the first ILD 有权
公开(公告)号：US09780113B2
公开(公告)日：2017-10-03
申请号：US14963803
申请日：2015-12-09
申请人： Jiwoon Im , Kwangchul Park , Jiyoun Seo , Jongmyeong Lee , Kyung-Tae Jang , Byungho Chun , Won-Seok Jung , Jongwan Choi , Tae-Jong Han
发明人： Jiwoon Im , Kwangchul Park , Jiyoun Seo , Jongmyeong Lee , Kyung-Tae Jang , Byungho Chun , Won-Seok Jung , Jongwan Choi , Tae-Jong Han
IPC分类号： H01L21/336 , H01L27/11582 , H01L27/1157 , H01L27/11575 , H01L21/768
CPC分类号： H01L27/11582 , H01L21/76837 , H01L27/1157 , H01L27/11575
摘要： A method for fabricating a semiconductor device includes forming a stacked structure on a substrate, forming a first interlayer dielectric covering the stacked structure, and forming a second interlayer dielectric covering the first interlayer dielectric. The stacked structure includes a stepwise shape. The first interlayer dielectric includes at least one step portion having a slope surface connecting a first top surface to a second top surface. The first top surface and the sloped surface define a first angle that is an obtuse angle. A level of the second top surface is higher than a level of the first top surface.

2. 发明授权

US09343475B2 Vertical memory devices and methods of manufacturing the same 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US09343475B2
公开(公告)日：2016-05-17
申请号：US14155842
申请日：2014-01-15
申请人： Kyung-Tae Jang , Sang-Hoon Lee , Ji-Youn Seo , Hyun-Yong Go , Koong-Hyun Nam , Ju-Wan Kim , Seung-Mok Shin , Myoung-Bum Lee , Ji-Woon Im , Tae-Jong Han
发明人： Kyung-Tae Jang , Sang-Hoon Lee , Ji-Youn Seo , Hyun-Yong Go , Koong-Hyun Nam , Ju-Wan Kim , Seung-Mok Shin , Myoung-Bum Lee , Ji-Woon Im , Tae-Jong Han
IPC分类号： H01L21/336 , H01L27/115 , H01L21/28
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/1157
摘要： In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes.
摘要翻译：在垂直存储器件的方法中，绝缘层和牺牲层在衬底上交替且重复地形成。通过绝缘层和暴露衬底顶表面的牺牲层形成一个孔。然后，可以扩大孔的内部。半导体图案形成为部分地填充孔的扩大部分。可以在孔和半导体图案的侧壁上形成阻挡层，电荷存储层和隧道绝缘层。然后，部分去除隧道绝缘层，电荷存储层和阻挡层，以露出半导体图案的顶表面。在半导体图案的暴露的顶表面和隧道绝缘层上形成沟道。牺牲层被栅电极代替。

3. 发明申请

US20150200203A1 Vertical Memory Devices and Methods of Manufacturing the Same 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US20150200203A1
公开(公告)日：2015-07-16
申请号：US14155842
申请日：2014-01-15
申请人： Kyung-Tae Jang , Sang-Hoon Lee , Ji-Youn Seo , Hyun-Yong Go , Koong-Hyun Nam , Ju-Wan Kim , Seung-Mok Shin , Myoung-Bum Lee , Ji-Woon Im , Tae-Jong Han
发明人： Kyung-Tae Jang , Sang-Hoon Lee , Ji-Youn Seo , Hyun-Yong Go , Koong-Hyun Nam , Ju-Wan Kim , Seung-Mok Shin , Myoung-Bum Lee , Ji-Woon Im , Tae-Jong Han
IPC分类号： H01L27/115 , H01L29/66 , H01L29/788 , H01L21/28
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/1157
摘要： In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes.
摘要翻译：在垂直存储器件的方法中，绝缘层和牺牲层在衬底上交替且重复地形成。通过绝缘层和暴露衬底顶表面的牺牲层形成一个孔。然后，可以扩大孔的内部。半导体图案形成为部分地填充孔的扩大部分。可以在孔和半导体图案的侧壁上形成阻挡层，电荷存储层和隧道绝缘层。然后，部分去除隧道绝缘层，电荷存储层和阻挡层，以露出半导体图案的顶表面。在半导体图案的暴露的顶表面和隧道绝缘层上形成沟道。牺牲层被栅电极代替。

4. 发明授权

US08440531B2 Methods of forming semiconductor memory devices having vertically stacked memory cells therein 有权
标题翻译：形成其中具有垂直堆叠的存储单元的半导体存储器件的方法
公开(公告)号：US08440531B2
公开(公告)日：2013-05-14
申请号：US13448582
申请日：2012-04-17
申请人： Tae-Jong Han , Daewoong Kim , Kyung-Tae Jang , Bongcheol Kim , Ohchel Kwon
发明人： Tae-Jong Han , Daewoong Kim , Kyung-Tae Jang , Bongcheol Kim , Ohchel Kwon
IPC分类号： H01L21/336
CPC分类号： H01L27/11582 , H01L29/7926
摘要： Methods of forming vertical nonvolatile memory devices utilize carbon-blocking sacrificial capping layers to increase device yield by reducing the likelihood that one or more vertically-stacked layers of materials will lift-off during fabrication. These capping layers may be provided to cover carbon-containing sacrificial layers that are highly polymerized.
摘要翻译：形成垂直非易失性存储器件的方法利用碳阻挡牺牲覆盖层来降低在制造期间一个或多个垂直堆叠的材料层将剥离的可能性。可以提供这些封盖层以覆盖高度聚合的含碳牺牲层。

5. 发明申请

US20120276719A1 METHODS OF FORMING SEMICONDUCTOR MEMORY DEVICES HAVING VERTICALLY STACKED MEMORY CELLS THEREIN 有权
标题翻译：形成具有垂直堆叠存储器电池的半导体存储器件的方法
公开(公告)号：US20120276719A1
公开(公告)日：2012-11-01
申请号：US13448582
申请日：2012-04-17
申请人： Tae-Jong Han , Daewoong Kim , Kyung-Tae Jang , Bongcheol Kim , Ohchel Kwon
发明人： Tae-Jong Han , Daewoong Kim , Kyung-Tae Jang , Bongcheol Kim , Ohchel Kwon
IPC分类号： H01L21/20 , H01L21/302
CPC分类号： H01L27/11582 , H01L29/7926
摘要： Methods of forming vertical nonvolatile memory devices utilize carbon-blocking sacrificial capping layers to increase device yield by reducing the likelihood that one or more vertically-stacked layers of materials will lift-off during fabrication. These capping layers may be provided to cover carbon-containing sacrificial layers that are highly polymerized.
摘要翻译：形成垂直非易失性存储器件的方法利用碳阻挡牺牲覆盖层来降低在制造期间一个或多个垂直堆叠的材料层将剥离的可能性。可以提供这些封盖层以覆盖高度聚合的含碳牺牲层。

6. 发明申请

US20140070300A1 VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US20140070300A1
公开(公告)日：2014-03-13
申请号：US13724187
申请日：2012-12-21
申请人： Kyung-Tae Jang , Myoung-Bum Lee , Ji-Youn Seo , Chang-Won Lee , Yong-Chae Jung , Woong-Hee Sohn
发明人： Kyung-Tae Jang , Myoung-Bum Lee , Ji-Youn Seo , Chang-Won Lee , Yong-Chae Jung , Woong-Hee Sohn
IPC分类号： H01L29/792 , H01L29/66
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/66666 , H01L29/66833 , H01L29/7926
摘要： A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.
摘要翻译：半导体器件包括衬底，垂直堆叠在衬底上的多个绝缘层，多个通道，布置在通过多个绝缘层中的至少一些形成的垂直开口中，以及多个部分交替地与多个绝缘体层在垂直方向。这些部分中的至少一些是相邻的多个通道的相应通道。每个部分包括形成在该部分的内壁上的导电阻挡图案，位于导电阻挡图案上的部分中的填充层图案，以及位于未被导电屏障占据部分的剩余区域中的栅电极或填充层图案。

7. 发明授权

US08643084B2 Vertical non-volatile memory device 有权
标题翻译：垂直非易失性存储器件
公开(公告)号：US08643084B2
公开(公告)日：2014-02-04
申请号：US13181622
申请日：2011-07-13
申请人： Seung-Mok Shin , Kyung-Tae Jang , Chang-Won Lee
发明人： Seung-Mok Shin , Kyung-Tae Jang , Chang-Won Lee
IPC分类号： H01L29/792
CPC分类号： H01L29/4234 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： A vertical non-volatile memory device includes a semiconductor pattern disposed on a substrate; and a plurality of transistors of first through n-th layers that are stacked on a side of the semiconductor pattern at predetermined distances from each other, wherein the transistors are spaced apart and insulated from one another at the predetermined distances via air gap, where n is a natural number equal to or greater than 2.
摘要翻译：垂直非易失性存储器件包括设置在衬底上的半导体图案; 以及第一至第n层的多个晶体管，其以预定距离彼此堆叠在所述半导体图案的一侧上，其中所述晶体管经由气隙以预定距离彼此间隔开并且彼此绝缘，其中n 是等于或大于2的自然数。

8. 发明申请

US20120064682A1 Methods of Manufacturing Three-Dimensional Semiconductor Memory Devices 审中-公开
标题翻译：制造三维半导体存储器件的方法
公开(公告)号：US20120064682A1
公开(公告)日：2012-03-15
申请号：US13230447
申请日：2011-09-12
申请人： Kyung-Tae Jang , Myoung Lee , Seungmok Shin , JinGyun Kim , Yeon-Sil Sohn , Seung-Yuo Lee , Dae-Hun Choi
发明人： Kyung-Tae Jang , Myoung Lee , Seungmok Shin , JinGyun Kim , Yeon-Sil Sohn , Seung-Yuo Lee , Dae-Hun Choi
IPC分类号： H01L21/8239
CPC分类号： H01L21/8239 , H01L21/02164 , H01L21/0217 , H01L21/02271 , H01L21/31111 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11578 , H01L27/11582 , H01L29/40114 , H01L29/40117
摘要： Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second material layers of at least 2n (n is an integer more than 2) are alternately and repeatedly stacked, on a substrate; wherein the first material layer applies a stress in a range of about 0.1×109 dyne/cm2 to about 10×109 dyne/cm2 to the substrate and the second material layer applies a stress in a range of about −0.1×109 dyne/cm2 to about −10×109 dyne/cm2 to the substrate.
摘要翻译：提供制造三维半导体器件的方法。该方法包括：在基板上形成薄膜结构，其中至少2n（n是大于2的整数）的第一和第二材料层交替重复堆叠; 其中所述第一材料层向所述基板施加约0.1×10 9达因/ cm 2至约10×10 9达因/ cm 2的范围内的应力，并且所述第二材料层施加约-0.1×109达因/ cm2的范围内的应力至约-10×109达因/平方厘米。

9. 发明申请

US20120012920A1 VERTICAL NON-VOLATILE MEMORY DEVICE 有权
标题翻译：垂直非易失性存储器件
公开(公告)号：US20120012920A1
公开(公告)日：2012-01-19
申请号：US13181622
申请日：2011-07-13
申请人： Seung-Mok SHIN , Kyung-Tae Jang , Chang-Won Lee
发明人： Seung-Mok SHIN , Kyung-Tae Jang , Chang-Won Lee
IPC分类号： H01L29/792
CPC分类号： H01L29/4234 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： A vertical non-volatile memory device includes a semiconductor pattern disposed on a substrate; and a plurality of transistors of first through n-th layers that are stacked on a side of the semiconductor pattern at predetermined distances from each other, wherein the transistors are spaced apart and insulated from one another at the predetermined distances via air gap, where n is a natural number equal to or greater than 2.
摘要翻译：垂直非易失性存储器件包括设置在衬底上的半导体图案; 以及第一至第n层的多个晶体管，其以预定距离彼此堆叠在所述半导体图案的一侧上，其中所述晶体管经由气隙以预定距离彼此间隔开并且彼此绝缘，其中n 是等于或大于2的自然数。

10. 发明申请

US20080111198A1 Stacked semiconductor device and method of manufacturing the same 审中-公开
标题翻译：叠层半导体器件及其制造方法
公开(公告)号：US20080111198A1
公开(公告)日：2008-05-15
申请号：US11978330
申请日：2007-10-29
申请人： Kyung-Tae Jang , Ju-Bum Lee , Jae-Kyo Chung , Heung-Seop Song , Mi-Young Lee
发明人： Kyung-Tae Jang , Ju-Bum Lee , Jae-Kyo Chung , Heung-Seop Song , Mi-Young Lee
IPC分类号： H01L27/088 , H01L21/8244
CPC分类号： H01L27/0688 , H01L27/088
摘要： A stacked semiconductor device includes a first gate structure formed on a substrate, a first insulating interlayer covering the first gate structure on the substrate, a first active pattern formed through and on the first insulating interlayer and contacting the substrate, a second gate structure formed on the first active pattern and the first insulating interlayer, a buffer layer covering the second gate structure on the first active pattern and the first insulating interlayer, a second insulating interlayer formed on the buffer layer, and a contact plug formed through the first and second insulating interlayers, which contacts with the substrate and is insulated from the second gate structure by the buffer layer. Operation failures of a transistor in the stacked semiconductor device can be reduced because the buffer layer prevents a word line from being electrically connected to the contact plug.
摘要翻译：叠层半导体器件包括：形成在衬底上的第一栅极结构，覆盖衬底上的第一栅极结构的第一绝缘层，形成在第一绝缘中间层上并在第一绝缘中间层上并与衬底接触的第一有源图案;第二栅极结构，第一有源图案和第一绝缘中间层，覆盖第一有源图案上的第二栅极结构和第一绝缘中间层的缓冲层，形成在缓冲层上的第二绝缘夹层，以及通过第一和第二绝缘体形成的接触塞中间层，其与衬底接触并且通过缓冲层与第二栅极结构绝缘。由于缓冲层防止字线电连接到接触插塞，所以可以减少叠层半导体器件中的晶体管的操作故障。

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