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1. 发明授权

US08643084B2 Vertical non-volatile memory device 有权
标题翻译：垂直非易失性存储器件
公开(公告)号：US08643084B2
公开(公告)日：2014-02-04
申请号：US13181622
申请日：2011-07-13
申请人： Seung-Mok Shin , Kyung-Tae Jang , Chang-Won Lee
发明人： Seung-Mok Shin , Kyung-Tae Jang , Chang-Won Lee
IPC分类号： H01L29/792
CPC分类号： H01L29/4234 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： A vertical non-volatile memory device includes a semiconductor pattern disposed on a substrate; and a plurality of transistors of first through n-th layers that are stacked on a side of the semiconductor pattern at predetermined distances from each other, wherein the transistors are spaced apart and insulated from one another at the predetermined distances via air gap, where n is a natural number equal to or greater than 2.
摘要翻译：垂直非易失性存储器件包括设置在衬底上的半导体图案; 以及第一至第n层的多个晶体管，其以预定距离彼此堆叠在所述半导体图案的一侧上，其中所述晶体管经由气隙以预定距离彼此间隔开并且彼此绝缘，其中n 是等于或大于2的自然数。

2. 发明申请

US20120012920A1 VERTICAL NON-VOLATILE MEMORY DEVICE 有权
标题翻译：垂直非易失性存储器件
公开(公告)号：US20120012920A1
公开(公告)日：2012-01-19
申请号：US13181622
申请日：2011-07-13
申请人： Seung-Mok SHIN , Kyung-Tae Jang , Chang-Won Lee
发明人： Seung-Mok SHIN , Kyung-Tae Jang , Chang-Won Lee
IPC分类号： H01L29/792
CPC分类号： H01L29/4234 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： A vertical non-volatile memory device includes a semiconductor pattern disposed on a substrate; and a plurality of transistors of first through n-th layers that are stacked on a side of the semiconductor pattern at predetermined distances from each other, wherein the transistors are spaced apart and insulated from one another at the predetermined distances via air gap, where n is a natural number equal to or greater than 2.
摘要翻译：垂直非易失性存储器件包括设置在衬底上的半导体图案; 以及第一至第n层的多个晶体管，其以预定距离彼此堆叠在所述半导体图案的一侧上，其中所述晶体管经由气隙以预定距离彼此间隔开并且彼此绝缘，其中n 是等于或大于2的自然数。

3. 发明申请

US20140070300A1 VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US20140070300A1
公开(公告)日：2014-03-13
申请号：US13724187
申请日：2012-12-21
申请人： Kyung-Tae Jang , Myoung-Bum Lee , Ji-Youn Seo , Chang-Won Lee , Yong-Chae Jung , Woong-Hee Sohn
发明人： Kyung-Tae Jang , Myoung-Bum Lee , Ji-Youn Seo , Chang-Won Lee , Yong-Chae Jung , Woong-Hee Sohn
IPC分类号： H01L29/792 , H01L29/66
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/66666 , H01L29/66833 , H01L29/7926
摘要： A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.
摘要翻译：半导体器件包括衬底，垂直堆叠在衬底上的多个绝缘层，多个通道，布置在通过多个绝缘层中的至少一些形成的垂直开口中，以及多个部分交替地与多个绝缘体层在垂直方向。这些部分中的至少一些是相邻的多个通道的相应通道。每个部分包括形成在该部分的内壁上的导电阻挡图案，位于导电阻挡图案上的部分中的填充层图案，以及位于未被导电屏障占据部分的剩余区域中的栅电极或填充层图案。

4. 发明授权

US08916922B2 Vertical memory devices and methods of manufacturing the same 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US08916922B2
公开(公告)日：2014-12-23
申请号：US13724187
申请日：2012-12-21
申请人： Kyung-Tae Jang , Myoung-Bum Lee , Ji-Youn Seo , Chang-Won Lee , Yong-Chae Jung , Woong-Hee Sohn
发明人： Kyung-Tae Jang , Myoung-Bum Lee , Ji-Youn Seo , Chang-Won Lee , Yong-Chae Jung , Woong-Hee Sohn
IPC分类号： H01L29/792 , H01L27/115 , H01L29/66
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/66666 , H01L29/66833 , H01L29/7926
摘要： A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.
摘要翻译：半导体器件包括衬底，垂直堆叠在衬底上的多个绝缘层，多个通道，布置在通过多个绝缘层中的至少一些形成的垂直开口中，以及多个部分交替地与多个绝缘体层在垂直方向。这些部分中的至少一些是相邻的多个通道的相应通道。每个部分包括形成在该部分的内壁上的导电阻挡图案，位于导电阻挡图案上的部分中的填充层图案，以及位于未被导电屏障占据部分的剩余区域中的栅电极或填充层图案。

5. 发明申请

US20090250752A1 Methods of fabricating semiconductor device having a metal gate pattern 有权
标题翻译：制造具有金属栅极图案的半导体器件的方法
公开(公告)号：US20090250752A1
公开(公告)日：2009-10-08
申请号：US12457323
申请日：2009-06-08
申请人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim
发明人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim
IPC分类号： H01L29/94 , H01L29/78
CPC分类号： H01L21/823437 , H01L21/28247 , H01L29/4941 , H01L29/6656
摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).
摘要翻译：提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。封盖层允许使用选择性氧化工艺，其可以是在富H2气氛中使用H 2 O和H 2的分压的湿式氧化工艺，以氧化基板和金属栅极图案的部分，同时抑制可以包括在金属栅极图案中的金属层的氧化。这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。

6. 发明授权

US07465617B2 Method of fabricating a semiconductor device having a silicon oxide layer, a method of fabricating a semiconductor device having dual spacers, a method of forming a silicon oxide layer on a substrate, and a method of forming dual spacers on a conductive material layer 有权
标题翻译：制造具有氧化硅层的半导体器件的方法，制造具有双间隔物的半导体器件的方法，在衬底上形成氧化硅层的方法以及在导电材料层上形成双间隔物的方法
公开(公告)号：US07465617B2
公开(公告)日：2008-12-16
申请号：US11269599
申请日：2005-11-09
申请人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Min-Chul Sun , Sun-Pil Youn
发明人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Min-Chul Sun , Sun-Pil Youn
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/02164 , H01L21/02211 , H01L21/02271 , H01L21/02362 , H01L21/31612 , H01L27/115
摘要： A method of fabricating a semiconductor device that includes dual spacers is provided. A nitrogen atmosphere may be created and maintained in a reaction chamber by supplying a nitrogen source gas. A silicon source gas and an oxygen source gas may then be supplied to the reaction chamber to deposit a silicon oxide layer on a semiconductor substrate, which may include a conductive material layer. A silicon nitride layer may then be formed on the silicon oxide layer by performing a general CVD process. Next, the silicon nitride layer may be etched until the silicon oxide layer is exposed. Because of the difference in etching selectivity between silicon nitride and silicon oxide, portions of the silicon nitride layer may remain on sidewalls of the conductive material layer. As a result, dual spacers formed of a silicon oxide layer and a silicon nitride layer may be formed on the sidewalls.
摘要翻译：提供一种制造包括双间隔件的半导体器件的方法。可以通过供应氮源气体在反应室中产生和保持氮气氛。然后可以将硅源气体和氧源气体供应到反应室以在可包括导电材料层的半导体衬底上沉积氧化硅层。然后可以通过执行一般CVD工艺在氧化硅层上形成氮化硅层。接下来，可以蚀刻氮化硅层直到氧化硅层露出。由于氮化硅和氧化硅之间的蚀刻选择性的差异，氮化硅层的部分可能残留在导电材料层的侧壁上。结果，可以在侧壁上形成由氧化硅层和氮化硅层形成的双重间隔物。

7. 发明申请

US20060186491A1 Methods of forming semiconductor devices having metal gate electrodes and related devices 审中-公开
标题翻译：形成具有金属栅电极的半导体器件和相关器件的方法
公开(公告)号：US20060186491A1
公开(公告)日：2006-08-24
申请号：US11384789
申请日：2006-03-20
申请人： Hee-Sook Park , Sun-Pil Youn , Chang-Won Lee
发明人： Hee-Sook Park , Sun-Pil Youn , Chang-Won Lee
IPC分类号： H01L29/94 , H01L21/3205
CPC分类号： H01L21/28114 , H01L21/28061 , H01L29/42376 , H01L29/4933 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： Methods of forming semiconductor devices and the devices so formed include forming an oxidation barrier pattern to cover sidewalls of a metal-containing pattern. The metal-containing pattern is located on a gate polysilicon layer and includes a metal silicide pattern, a metal barrier pattern and a gate metal pattern which are sequentially stacked. An oxide layer is not formed between the metal barrier pattern and the gate polysilicon pattern. Furthermore, a metal silicide pattern located between the metal barrier pattern and the gate polysilicon pattern functions not only as an ohmic layer decreasing a contact resistance between the metal barrier pattern and the gate polysilicon pattern but also as an oxidation barrier to prevent a metal such as tungsten from being oxidized. Therefore, semiconductor devices have improved operational speed and/or reliability.
摘要翻译：形成半导体器件的方法和如此形成的器件包括形成氧化阻挡图案以覆盖含金属图案的侧壁。含金属图案位于栅极多晶硅层上，并且包括依次层叠的金属硅化物图案，金属阻挡图案和栅极金属图案。在金属阻挡图案和栅极多晶硅图案之间不形成氧化物层。此外，位于金属阻挡图案和栅极多晶硅图案之间的金属硅化物图案不仅用作降低金属阻挡图案和栅极多晶硅图案之间的接触电阻的欧姆层，而且还作为防止金属如钨被氧化。因此，半导体器件具有改进的操作速度和/或可靠性。

8. 发明申请

US20060163677A1 Methods of forming a semiconductor device having a metal gate electrode and associated devices 审中-公开
公开(公告)号：US20060163677A1
公开(公告)日：2006-07-27
申请号：US11386644
申请日：2006-03-22
申请人： Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim , Si-Young Choi , Gil-Heyun Choi , Ja-Hum Ku , Chang-Won Lee , Jong-Myeong Lee , Kwon-Sun Ryu
发明人： Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim , Si-Young Choi , Gil-Heyun Choi , Ja-Hum Ku , Chang-Won Lee , Jong-Myeong Lee , Kwon-Sun Ryu
IPC分类号： H01L29/94
CPC分类号： H01L21/28061 , H01L21/28088 , H01L29/4941 , H01L29/4966 , H01L29/6659 , H01L29/7833
摘要： Methods of forming a semiconductor device having a metal gate electrode include sequentially forming a gate insulator, a gate polysilicon layer and a metal-gate layer on a semiconductor substrate. The metal-gate layer and the gate polysilicon layer are sequentially patterned to form a gate pattern comprising a stacked gate polysilicon pattern and a metal-gate pattern. An oxidation barrier layer is formed to cover at least a portion of a sidewall of the metal-gate pattern.

9. 发明申请

US20060110900A1 Method of forming a gate of a semiconductor device 有权
标题翻译：形成半导体器件的栅极的方法
公开(公告)号：US20060110900A1
公开(公告)日：2006-05-25
申请号：US11283121
申请日：2005-11-18
申请人： Sun-Pil Youn , Chang-Won Lee , Woong-Hee Sohn , Gil-Heyun Choi , Jong-Ryeol Yoo , Jang-Hee Lee , Jae-Hwa Park , Dong-Chan Lim , Byung-Hak Lee , Hee-Sook Park
发明人： Sun-Pil Youn , Chang-Won Lee , Woong-Hee Sohn , Gil-Heyun Choi , Jong-Ryeol Yoo , Jang-Hee Lee , Jae-Hwa Park , Dong-Chan Lim , Byung-Hak Lee , Hee-Sook Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/28247 , H01L21/28044 , H01L29/4925
摘要： In a method for forming a gate in a semiconductor device, a first preliminary gate structure is formed on a substrate. The first preliminary gate structure includes a gate oxide layer, a polysilicon layer pattern and a tungsten layer pattern sequentially stacked on the substrate. A primary oxidation process is performed using oxygen radicals at a first temperature for adjusting a thickness of the gate oxide layer to form a second preliminary gate structure having tungsten oxide. The tungsten oxide is reduced to a tungsten material using a gas containing hydrogen to form a gate structure. The tungsten oxide may not be formed on the gate structure so that generation of the whiskers may be suppressed. Thus, a short between adjacent wirings may not be generated.
摘要翻译：在半导体器件中形成栅极的方法中，在衬底上形成第一预栅极结构。第一预选栅极结构包括依次层叠在基板上的栅极氧化物层，多晶硅层图案和钨层图案。在第一温度下使用氧自由基进行一次氧化处理，以调节栅极氧化物层的厚度以形成具有氧化钨的第二初步栅极结构。使用含氢气体将钨氧化物还原成钨材料以形成栅极结构。在栅极结构上可能不形成氧化钨，从而可以抑制晶须的产生。因此，可能不会产生相邻布线之间的短路。

10. 发明申请

US20060057807A1 Method of fabricating a semiconductor device having a silicon oxide layer, a method of fabricating a semiconductor device having dual spacers, a method of forming a silicon oxide layer on a substrate, and a method of forming dual spacers on a conductive material layer 有权
公开(公告)号：US20060057807A1
公开(公告)日：2006-03-16
申请号：US11269599
申请日：2005-11-09
申请人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Min-Chul Sun , Sun-Pil Youn
发明人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Min-Chul Sun , Sun-Pil Youn
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/02164 , H01L21/02211 , H01L21/02271 , H01L21/02362 , H01L21/31612 , H01L27/115
摘要： A method of fabricating a semiconductor device that includes dual spacers is provided. A nitrogen atmosphere may be created and maintained in a reaction chamber by supplying a nitrogen source gas. A silicon source gas and an oxygen source gas may then be supplied to the reaction chamber to deposit a silicon oxide layer on a semiconductor substrate, which may include a conductive material layer. A silicon nitride layer may then be formed on the silicon oxide layer by performing a general CVD process. Next, the silicon nitride layer may be etched until the silicon oxide layer is exposed. Because of the difference in etching selectivity between silicon nitride and silicon oxide, portions of the silicon nitride layer may remain on sidewalls of the conductive material layer. As a result, dual spacers formed of a silicon oxide layer and a silicon nitride layer may be formed on the sidewalls.

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