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1. 发明授权

US4403392A Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US4403392A
公开(公告)日：1983-09-13
申请号：US152305
申请日：1980-05-22
申请人： Jiro Oshima , Masaharu Aoyama , Seiji Yasuda , Toshio Yonezawa
发明人： Jiro Oshima , Masaharu Aoyama , Seiji Yasuda , Toshio Yonezawa
IPC分类号： H01L29/43 , H01L21/225 , H01L21/28 , H01L21/321 , H01L23/522 , H01L23/532
CPC分类号： H01L23/53271 , H01L21/2257 , H01L21/28 , H01L21/321 , H01L23/5226 , H01L2924/0002 , Y10S438/92
摘要： A method for manufacturing a semiconductor device having a high breakdown voltage and a high reliability, comprises (a) forming on a semiconductor substrate an insulating layer having a diffusion window; (b) forming an impurity-doped poly-silicon layer on the insulating layer and on that portion of the semiconductor substrate which is exposed through the diffusion window; (c) forming an undoped poly-silicon layer on the impurity-doped poly-silicon layer; (d) thermally oxidizing the substrate with the insulating layer, impurity-doped poly-silicon layer and undoped poly-silicon layer, thus diffusing the impurity from the impurity-doped poly-silicon layer into the semiconductor substrate through the diffusion window and converting the undoped poly-silicon layer to a silicon oxide layer; (e) forming on the silicon oxide layer an oxidation-resisting mask layer in a desired pattern; and (f) thermally oxidizing the substrate with the insulating layer, impurity-doped poly-silicon layer, silicon oxide layer and mask layer, thus converting those portions of the impurity-doped poly-silicon layer which lie beneath those portions of the silicon oxide layer which are exposed through the mask layer to impurity-doped silicon oxide layers, whereby the remaining portions of the impurity-doped poly-silicon layer provide an interconnection electrode layer having a desired pattern.
摘要翻译：一种制造具有高击穿电压和高可靠性的半导体器件的方法，包括：（a）在半导体衬底上形成具有扩散窗的绝缘层; （b）在绝缘层上形成掺杂杂质的多晶硅层，以及通过扩散窗露出的部分半导体衬底; （c）在杂质掺杂的多晶硅层上形成未掺杂的多晶硅层; （d）用绝缘层，杂质掺杂的多晶硅层和未掺杂的多晶硅层热氧化衬底，从而通过扩散窗将杂质从杂质掺杂的多晶硅层扩散到半导体衬底中，并将未掺杂的多晶硅层到氧化硅层; （e）在所述氧化硅层上形成所需图案的抗氧化掩模层; 和（f）用绝缘层，杂质掺杂的多晶硅层，氧化硅层和掩模层热氧化衬底，从而转换位于氧化硅部分之下的杂质掺杂多晶硅层的那些部分层，其通过掩模层暴露于杂质掺杂的氧化硅层，由此杂质掺杂多晶硅层的剩余部分提供具有期望图案的互连电极层。

2. 发明授权

US4636832A Semiconductor device with an improved bonding section 失效
标题翻译：具有改进的接合部分的半导体器件
公开(公告)号：US4636832A
公开(公告)日：1987-01-13
申请号：US837663
申请日：1986-03-04
申请人： Masahiro Abe , Masaharu Aoyama , Takashi Ajima , Toshio Yonezawa
发明人： Masahiro Abe , Masaharu Aoyama , Takashi Ajima , Toshio Yonezawa
IPC分类号： H01L21/60 , H01L23/485 , H01L23/532 , H01L23/14
CPC分类号： H01L24/85 , H01L23/5329 , H01L24/05 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05558 , H01L2224/05624 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48724 , H01L2224/85 , H01L24/45 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/12036 , H01L2924/19043 , H01L2924/20752
摘要： A semiconductor device with a bonding section comprising a semiconductor substrate, a silicon layer formed on the semiconductor substrate with a first insulating layer interposed therebetween, and a bonding pad formed on the silicon layer with a second insulating layer interposed therebetween. The silicon layer has substantially the same size as the bonding pad. When a lead line is bonded to the bonding pad, the silicon layer lessens the stress caused by the bonding.
摘要翻译：一种具有接合部分的半导体器件，包括半导体衬底，在半导体衬底上形成有第一绝缘层的硅层，以及形成在硅层上并具有介于其间的第二绝缘层的接合焊盘。硅层具有与焊盘大致相同的尺寸。当引线与接合焊盘接合时，硅层减小由接合引起的应力。

3. 发明授权

US4561009A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4561009A
公开(公告)日：1985-12-24
申请号：US554336
申请日：1983-11-22
申请人： Toshio Yonezawa , Masaharu Aoyama
发明人： Toshio Yonezawa , Masaharu Aoyama
IPC分类号： H01L21/316 , H01L23/532 , H01L21/283 , H01L23/08 , H01L23/54
CPC分类号： H01L21/02244 , H01L21/02142 , H01L21/02145 , H01L21/02161 , H01L21/02175 , H01L21/02178 , H01L21/02194 , H01L21/02203 , H01L21/02258 , H01L21/02266 , H01L21/31616 , H01L21/31687 , H01L23/53219 , H01L23/5329 , H01L2924/0002 , Y10S438/937
摘要： A semiconductor device is disclosed which includes a semiconductor substrate; a metal wiring layer comprising an Al alloy formed on the surface of this substrate; and an alumina layer covering this metal layer and containing at least one metal selected from the group consisting of Cu, Mg, Ni, Cr, Mn, Ti and Y. A method for manufacturing such a semiconductor device is also disclosed.
摘要翻译：公开了一种半导体器件，其包括半导体衬底; 在该基板的表面上形成有Al合金的金属配线层; 以及覆盖该金属层并含有选自Cu，Mg，Ni，Cr，Mn，Ti和Y中的至少一种金属的氧化铝层。还公开了制造这种半导体器件的方法。

4. 发明授权

US4200969A Semiconductor device with multi-layered metalizations 失效
标题翻译：具有多层金属化的半导体器件
公开(公告)号：US4200969A
公开(公告)日：1980-05-06
申请号：US831873
申请日：1977-09-09
申请人： Masaharu Aoyama , Shunichi Hiraki , Toshio Yonezawa
发明人： Masaharu Aoyama , Shunichi Hiraki , Toshio Yonezawa
IPC分类号： H01L21/3205 , H01L21/306 , H01L21/3213 , H01L21/768 , B01J17/00
CPC分类号： H01L21/76838 , H01L21/32134 , H01L21/32136 , Y10S438/945 , Y10T29/49156
摘要： There are provided a semiconductor device having alternately layered insulating and conductive layers on the major surface of a semiconductor body and the process for manufacturing the semiconductor device. In the manufacturing process, the conductive layers other than the conductive layer finally formed are each formed to be a laminate including at least two metal layers of which the etching rates are different. The photo-engraving process follows this step. In the lamina, the metal layer closer to the semiconductor body has a lower etching rate than that of the metal layer formed thereover. In the semiconductor device, the conductive layer other than that disposed furthest away from the semiconductor body has its side wall diverged to widen toward the semiconductor body.
摘要翻译：提供了一种在半导体主体的主表面上具有交替层叠的绝缘和导电层的半导体器件和用于制造半导体器件的工艺。在制造过程中，最终形成的导电层以外的导电层各自形成为包括蚀刻速率不同的至少两个金属层的层压体。照相雕刻过程遵循此步骤。在薄层中，更靠近半导体本体的金属层的蚀刻速率比形成在其上的金属层的蚀刻速率低。在半导体器件中，除了远离半导体主体的导电层之外的导电层的侧壁发散，朝向半导体本体变宽。

5. 发明授权

US4520041A Method for forming metallization structure having flat surface on semiconductor substrate 失效
标题翻译：在半导体衬底上形成具有平坦表面的金属化结构的方法
公开(公告)号：US4520041A
公开(公告)日：1985-05-28
申请号：US548440
申请日：1983-11-03
申请人： Masaharu Aoyama , Masahiro Abe , Takashi Ajima , Toshio Yonezawa
发明人： Masaharu Aoyama , Masahiro Abe , Takashi Ajima , Toshio Yonezawa
IPC分类号： H01L21/3205 , H01L21/306 , H01L21/768 , H01L23/532 , H01L21/283 , H01L21/302
CPC分类号： H01L23/53295 , H01L21/7684 , H01L23/5329 , H01L2924/0002
摘要： A metallization structure having a substantially flat surface can be formed on a semiconductor substrate by forming first and second insulating layers on the substrate. The second insulating layer is selectively removed to form grooves therein. Then, a metallic material layer is conformably formed. The metallic layer has grooves corresponding to the grooves of the second insulating layer. A flowable polymer is applied to the surface of the resultant structure to form a layer having a flat surface. The polymer layer and the metallic layer are sequentially ion-etched to expose the second insulating layer. Thus, the metallization structure constituted by the remaining metallic layer and the second insulating layer is formed to have a flat surface.
摘要翻译：通过在衬底上形成第一绝缘层和第二绝缘层，可以在半导体衬底上形成具有基本平坦表面的金属化结构。选择性地去除第二绝缘层以在其中形成凹槽。然后，顺应地形成金属材料层。金属层具有与第二绝缘层的槽对应的槽。将可流动的聚合物施加到所得结构的表面以形成具有平坦表面的层。依次离子蚀刻聚合物层和金属层以露出第二绝缘层。因此，由剩余的金属层和第二绝缘层构成的金属化结构形成为具有平坦的表面。

6. 发明授权

US4507673A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4507673A
公开(公告)日：1985-03-26
申请号：US534361
申请日：1983-09-21
申请人： Masaharu Aoyama , Shunichi Hiraki , Toshio Yonezawa
发明人： Masaharu Aoyama , Shunichi Hiraki , Toshio Yonezawa
IPC分类号： H01L27/112 , H01L21/8246 , H01L21/8247 , H01L29/51 , H01L29/788 , H01L29/792 , H01L29/78
CPC分类号： H01L29/513 , H01L29/51 , H01L29/792
摘要： A semiconductor memory device is disclosed which comprises:a semiconductor substrate of n conductivity type;source and drain regions of p.sup.+ conductivity type formed in the substrate;a first gate insulation film of silicon dioxide (SiO.sub.2) formed on the substrate; anda second gate insulation film of silicon carbide (SiC) formed on the first gate insulation film.
摘要翻译：公开了一种半导体存储器件，其包括：n导电类型的半导体衬底; 在衬底中形成p +导电类型的源区和漏区; 在基板上形成的二氧化硅（SiO 2）的第一栅极绝缘膜; 以及形成在第一栅极绝缘膜上的碳化硅（SiC）的第二栅极绝缘膜。

7. 发明授权

US4433004A Semiconductor device and a method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US4433004A
公开(公告)日：1984-02-21
申请号：US166182
申请日：1980-07-07
申请人： Toshio Yonezawa , Masaharu Aoyama
发明人： Toshio Yonezawa , Masaharu Aoyama
IPC分类号： H01L21/316 , H01L23/532 , H01L21/283 , H01L21/314
CPC分类号： H01L21/02244 , H01L21/02142 , H01L21/02145 , H01L21/02161 , H01L21/02175 , H01L21/02178 , H01L21/02194 , H01L21/02203 , H01L21/02258 , H01L21/02266 , H01L21/31616 , H01L21/31687 , H01L23/53219 , H01L23/5329 , H01L2924/0002 , Y10S438/937
摘要： A semiconductor device is disclosed which includes a semiconductor substrate; a metal wiring layer comprising an Al alloy formed on the surface of this substrate; and an alumina layer covering this metal layer and containing at least one metal selected from the group consisting of Cu, Mg, Ni, Cr, Mn, Ti and Y. A method for manufacturing such a semiconductor device is also disclosed.
摘要翻译：公开了一种半导体器件，其包括半导体衬底; 在该基板的表面上形成有Al合金的金属配线层; 以及覆盖该金属层并含有选自Cu，Mg，Ni，Cr，Mn，Ti和Y中的至少一种金属的氧化铝层。还公开了制造这种半导体器件的方法。

8. 发明授权

US4334349A Method of producing semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US4334349A
公开(公告)日：1982-06-15
申请号：US155975
申请日：1980-06-03
申请人： Masaharu Aoyama , Jiro Ohshima , Toshio Yonezawa
发明人： Masaharu Aoyama , Jiro Ohshima , Toshio Yonezawa
IPC分类号： H01L21/3205 , H01L21/033 , H01L21/768 , H01L23/31 , H01L23/482 , H01L23/532 , H01L21/225 , B44C1/22 , H01L21/312
CPC分类号： H01L23/4827 , H01L21/033 , H01L21/76838 , H01L21/7688 , H01L23/3192 , H01L23/5329 , H01L23/53295 , H01L2924/0002
摘要： Disclosed is a method of producing a semiconductor device, comprising the steps of (a) forming a first insulating layer consisting of a lower silicon oxide film and an upper slicon nitride film on the surface of a semiconductor substrate, (b) forming a second insulating layer consisting of silicon oxide on the first insulating layer, (c) forming a third insulating layer consisting of silicon nitride on the second insulating layer, (d) selectively removing the third insulating layer so as to form a mask used for forming a hole for an interconnection electrode, (e) etching away the exposed portion of the second insulating layer by using the mask so as to form the hole for the interconnection electrode, (f) forming a conductive material layer on the entire surface of the structure obtained by step (e), a contact hole formed in the first insulating layer after step (a) or (e) being filled with the conductive material so as to allow the conductive material layer disposed on the first insulating layer to be connected to the semiconductor substrate, and (g) removing the second insulating layer by etching so as to lift-off the third insulating layer and the conductive material layer laminated on the second insulating layer, the remaining conductive materal layer providing the interconnection electrode.
摘要翻译：公开了一种制造半导体器件的方法，包括以下步骤：（a）在半导体衬底的表面上形成由下部氧化硅膜和上部氮化硅膜构成的第一绝缘层，（b）形成第二绝缘体在所述第一绝缘层上由氧化硅构成的层，（c）在所述第二绝缘层上形成由氮化硅构成的第三绝缘层，（d）选择性地除去所述第三绝缘层，以形成用于形成用于互连电极，（e）通过使用掩模蚀刻掉第二绝缘层的暴露部分，以便形成用于互连电极的孔，（f）在通过步骤获得的结构的整个表面上形成导电材料层（e）中，在步骤（a）或（e）之后形成在第一绝缘层中的接触孔填充有导电材料，以便允许设置在第一岛上的导电材料层以及（g）通过蚀刻去除第二绝缘层，以便剥离层压在第二绝缘层上的第三绝缘层和导电材料层，剩余的导电侧层提供互连电极。

9. 发明授权

US4618878A Semiconductor device having a multilayer wiring structure using a polyimide resin 失效
标题翻译：具有使用聚酰亚胺树脂的多层布线结构的半导体装置
公开(公告)号：US4618878A
公开(公告)日：1986-10-21
申请号：US621086
申请日：1984-06-15
申请人： Masaharu Aoyama , Masahiro Abe , Takashi Ajima , Toshio Yonezawa
发明人： Masaharu Aoyama , Masahiro Abe , Takashi Ajima , Toshio Yonezawa
IPC分类号： H01L21/768 , H01L21/31 , H01L23/522 , H01L23/532 , H01L23/48
CPC分类号： H01L23/5329 , H01L2924/0002
摘要： A semiconductor device having a multilayer wiring structure which comprises a semiconductor substrate, a first wiring layer deposited on said substrate, and a second wiring layer deposited on said first wiring layer with insulating layers disposed therebetween, wherein the insulating interlayer consists of an inorganic insulating layer and a polyimide-based resin film overlying the inorganic insulating layer. The thickness ratio of the polyimide-based resin film to the inorganic insulating film ranges from 0.1 to 0.5. A method of manufacturing a semiconductor device of a multilayer wiring structure wherein an opening is formed in the insulating interlayer to have a small step.
摘要翻译：一种具有多层布线结构的半导体器件，包括半导体衬底，沉积在所述衬底上的第一布线层和沉积在所述第一布线层上的绝缘层的第二布线层，其中绝缘中间层由无机绝缘层以及覆盖无机绝缘层的聚酰亚胺系树脂膜。聚酰亚胺系树脂膜与无机绝缘膜的厚度比为0.1〜0.5。一种制造多层布线结构的半导体器件的方法，其中在绝缘中间层中形成具有小台阶的开口。

10. 发明授权

US4462856A System for etching a metal film on a semiconductor wafer 失效
标题翻译：用于蚀刻半导体晶片上的金属膜的系统
公开(公告)号：US4462856A
公开(公告)日：1984-07-31
申请号：US467298
申请日：1983-02-17
申请人： Masahiro Abe , Toshio Yonezawa , Masaharu Aoyama , Takashi Ajima
发明人： Masahiro Abe , Toshio Yonezawa , Masaharu Aoyama , Takashi Ajima
IPC分类号： C23F1/00 , H01L21/306 , H01L21/3213 , C23F1/02 , C25F3/04 , C25F3/12
CPC分类号： C23F1/00 , H01L21/306 , H01L21/32134
摘要： A system is adapted to etch an aluminium film on a semiconductor wafer into a predetermined pattern by immersing the film in an etching solution. The system comprises a voltage detecting circuit for detecting a voltage created between a platinum electrode and the aluminium film on the semiconductor wafer which are immersed in the etching solution, a comparator for comparing a reference voltage with the voltage detected by the voltage detecting circuit to produce an output signal, and a timer for starting a time count operation upon receipt of the output signal from the comparator and for producing an etching completion signal when it continuously receives the output signal from the comparator for a predetermined time period.
摘要翻译：系统适于通过将膜浸入蚀刻溶液中将半导体晶片上的铝膜蚀刻成预定图案。该系统包括电压检测电路，用于检测浸在蚀刻溶液中的铂电极和半导体晶片上的铝膜之间产生的电压;比较器，用于将参考电压与由电压检测电路检测到的电压进行比较，以产生输出信号，以及在从比较器接收到输出信号时开始时间计数操作的定时器，并且当其在预定时间段内连续接收来自比较器的输出信号时产生蚀刻完成信号。

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