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1. 发明授权

US07732313B2 FUSI integration method using SOG as a sacrificial planarization layer 有权
标题翻译：使用SOG作为牺牲平坦化层的FUSI积分方法
公开(公告)号：US07732313B2
公开(公告)日：2010-06-08
申请号：US12348660
申请日：2009-01-05
申请人： Jiong-Ping Lu , Yaw S. Obeng , Ping Jiang , Joe G. Tran
发明人： Jiong-Ping Lu , Yaw S. Obeng , Ping Jiang , Joe G. Tran
IPC分类号： H01L21/44
CPC分类号： H01L21/31055 , H01L21/28097 , H01L21/32134 , H01L29/4975 , H01L29/6656 , H01L29/7833
摘要： A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.
摘要翻译：一种制造晶体管20的方法，其包括使用过渡金属氮化物层200和/或SOG层220来保护源极/漏极区域60在栅电极90的硅化期间不被硅化。SOG层210被平坦化以暴露在栅极硅化处理之前的过渡金属氮化物层200或栅电极93。如果使用过渡金属氮化物层200，则在栅电极90完全硅化之前，从栅电极93的顶部去除它。

2. 发明授权

US07943499B2 FUSI integration method using SOG as a sacrificial planarization layer 有权
标题翻译：使用SOG作为牺牲平坦化层的FUSI积分方法
公开(公告)号：US07943499B2
公开(公告)日：2011-05-17
申请号：US12603169
申请日：2009-10-21
申请人： Jiong-Ping Lu , Yaw S. Obeng , Ping Jiang , Joe G. Tran
发明人： Jiong-Ping Lu , Yaw S. Obeng , Ping Jiang , Joe G. Tran
IPC分类号： H01L21/28 , H01L21/44
CPC分类号： H01L21/31055 , H01L21/28097 , H01L21/32134 , H01L29/4975 , H01L29/6656 , H01L29/7833
摘要： A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.
摘要翻译：一种制造晶体管20的方法，其包括使用过渡金属氮化物层200和/或SOG层220来保护源极/漏极区域60在栅电极90的硅化期间不被硅化。SOG层210被平坦化以暴露在栅极硅化处理之前的过渡金属氮化物层200或栅电极93。如果使用过渡金属氮化物层200，则在栅电极90完全硅化之前，从栅电极93的顶部去除它。

3. 发明授权

US07732312B2 FUSI integration method using SOG as a sacrificial planarization layer 有权
公开(公告)号：US07732312B2
公开(公告)日：2010-06-08
申请号：US11338028
申请日：2006-01-24
申请人： Jiong-Ping Lu , Yaw S. Obeng , Ping Jiang , Joe G. Tran
发明人： Jiong-Ping Lu , Yaw S. Obeng , Ping Jiang , Joe G. Tran
IPC分类号： H01L21/44
CPC分类号： H01L21/31055 , H01L21/28097 , H01L21/32134 , H01L29/4975 , H01L29/6656 , H01L29/7833
摘要： A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.

4. 发明申请

US20100041231A1 FUSI Integration Method Using SOG as a Sacrificial Planarization Layer 有权
标题翻译：使用SOG作为牺牲平面化层的FUSI集成方法
公开(公告)号：US20100041231A1
公开(公告)日：2010-02-18
申请号：US12603169
申请日：2009-10-21
申请人： Jiong-Ping Lu , Yaw S. Obeng , Ping Jiang , Joe G. Tran
发明人： Jiong-Ping Lu , Yaw S. Obeng , Ping Jiang , Joe G. Tran
IPC分类号： H01L21/30
CPC分类号： H01L21/31055 , H01L21/28097 , H01L21/32134 , H01L29/4975 , H01L29/6656 , H01L29/7833
摘要： A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.
摘要翻译：一种制造晶体管20的方法，其包括使用过渡金属氮化物层200和/或SOG层220来保护源极/漏极区域60在栅电极90的硅化期间不被硅化。SOG层210被平坦化以暴露在栅极硅化处理之前的过渡金属氮化物层200或栅电极93。如果使用过渡金属氮化物层200，则在栅电极90完全硅化之前，从栅电极93的顶部去除。

5. 发明申请

US20090111224A1 FUSI INTEGRATION METHOD USING SOG AS A SACRIFICIAL PLANARIZATION LAYER 有权
标题翻译：使用SOG作为一个正规平面化层的FUSI集成方法
公开(公告)号：US20090111224A1
公开(公告)日：2009-04-30
申请号：US12348660
申请日：2009-01-05
申请人： Jiong-Ping Lu , Yew S. Obeng , Ping Jiang , Joe G. Tran
发明人： Jiong-Ping Lu , Yew S. Obeng , Ping Jiang , Joe G. Tran
IPC分类号： H01L21/18
CPC分类号： H01L21/31055 , H01L21/28097 , H01L21/32134 , H01L29/4975 , H01L29/6656 , H01L29/7833
摘要： A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.
摘要翻译：一种制造晶体管20的方法，其包括使用过渡金属氮化物层200和/或SOG层220来保护源极/漏极区域60在栅电极90的硅化期间不被硅化。SOG层210被平坦化以暴露在栅极硅化处理之前的过渡金属氮化物层200或栅电极93。如果使用过渡金属氮化物层200，则在栅电极90完全硅化之前，从栅电极93的顶部去除它。

6. 发明申请

US20070173047A1 FUSI integration method using SOG as a sacrificial planarization layer 有权
标题翻译：使用SOG作为牺牲平坦化层的FUSI积分方法
公开(公告)号：US20070173047A1
公开(公告)日：2007-07-26
申请号：US11338028
申请日：2006-01-24
申请人： Jiong-Ping Lu , Yaw Obeng , Ping Jiang , Joe Tran
发明人： Jiong-Ping Lu , Yaw Obeng , Ping Jiang , Joe Tran
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L21/31055 , H01L21/28097 , H01L21/32134 , H01L29/4975 , H01L29/6656 , H01L29/7833
摘要： A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.
摘要翻译：制造晶体管20的方法包括使用过渡金属氮化物层200和/或SOG层220来保护源极/漏极区域60在栅电极90的硅化期间不被硅化。在栅极硅化处理之前，SOG层210被平坦化以暴露过渡金属氮化物层200或栅电极93。如果使用过渡金属氮化物层200，则在栅电极90完全硅化之前，从栅电极93的顶部去除它。

7. 发明申请

US20070063294A1 Semiconductor Device Having a Fully Silicided Gate Electrode and Method of Manufacture Therefor 审中-公开
标题翻译：具有全硅酸盐栅电极的半导体器件及其制造方法
公开(公告)号：US20070063294A1
公开(公告)日：2007-03-22
申请号：US11556834
申请日：2006-11-06
申请人： Haowen Bu , Jiong-Ping Lu , Shaofeng Yu , Ping Jiang , Clint Montgomery
发明人： Haowen Bu , Jiong-Ping Lu , Shaofeng Yu , Ping Jiang , Clint Montgomery
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00 , H01L27/108 , H01L31/119
CPC分类号： H01L29/66507 , H01L21/28097 , H01L21/823835 , H01L21/823864 , H01L29/4975 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a silicided gate electrode (150) located over a substrate (110), the silicided gate electrode (150) having gate sidewall spacers (160) located on sidewalls thereof. The semiconductor device (100) further includes source/drain regions (170) located in the substrate (110) proximate the silicided gate electrode (150), and silicided source/drain regions (180) located in the source/drain regions (170) and at least partially under the gate sidewall spacers (160).
摘要翻译：本发明提供一种半导体器件及其制造方法以及集成电路的制造方法。除了其它可能的元件之外，半导体器件（100）包括位于衬底（110）上方的硅化栅电极（150），硅化栅电极（150）具有位于其侧壁上的栅极侧壁间隔物（160）。半导体器件（100）还包括位于靠近硅化物栅电极（150）的衬底（110）中的源/漏区（170）和位于源/漏区（170）中的硅化源/漏区（180）并且至少部分地在栅极侧壁间隔件（160）下方。

8. 发明授权

US07183187B2 Integration scheme for using silicided dual work function metal gates 有权
标题翻译：使用硅化双功能金属门的集成方案
公开(公告)号：US07183187B2
公开(公告)日：2007-02-27
申请号：US10851750
申请日：2004-05-20
申请人： Jiong-Ping Lu , Gregory Shinn , Ping Jiang
发明人： Jiong-Ping Lu , Gregory Shinn , Ping Jiang
IPC分类号： H01L21/3205
CPC分类号： H01L29/66507 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L27/0811 , H01L28/60
摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device, among other possible steps, includes forming a polysilicon gate electrode (250) over a substrate (210) and forming source/drain regions (610) in the substrate (210) proximate the polysilicon gate electrode (250). The method further includes forming a protective layer (710) over the source/drain regions (610) and the polysilicon gate electrode (250), then removing the protective layer (710) from over a top surface of the polysilicon gate electrode (250) while leaving the protective layer (710) over the source/drain regions (250). After the protective layer (710) has been removed from over the top surface of the polysilicon gate electrode (250), the polysilicon gate electrode (250) is silicided to form a silicided gate electrode (1310). The protective layer (710) is also removed from over the source/drain regions (610) and source/drain contact regions (1610) are formed.
摘要翻译：本发明提供一种制造半导体器件的方法及其制造方法，该集成电路包括该半导体器件。除了其他可能的步骤之外，制造半导体器件的方法包括在衬底（210）上形成多晶硅栅电极（250），并在靠近多晶硅栅电极（250）的衬底（210）中形成源/漏区（610））。该方法还包括在源极/漏极区域（610）和多晶硅栅电极（250）之上形成保护层（710），然后从多晶硅栅电极（250）的顶表面上方移除保护层（710）同时将保护层（710）留在源/漏区（250）上。在保护层（710）已从多晶硅栅电极（250）的顶表面上方移除之后，多晶硅栅电极（250）被硅化以形成硅化栅电极（1310）。保护层（710）也从源极/漏极区域（610）上去除并形成源极/漏极接触区域（1610）。

9. 发明申请

US20050215055A1 Semiconductor device having a fully silicided gate electrode and method of manufacture therefor 有权
标题翻译：具有全硅化物栅电极的半导体器件及其制造方法
公开(公告)号：US20050215055A1
公开(公告)日：2005-09-29
申请号：US10808168
申请日：2004-03-24
申请人： Haowen Bu , Jiong-Ping Lu , Shaofeng Yu , Ping Jiang , Clint Montgomery
发明人： Haowen Bu , Jiong-Ping Lu , Shaofeng Yu , Ping Jiang , Clint Montgomery
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66507 , H01L21/28097 , H01L21/823835 , H01L21/823864 , H01L29/4975 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a silicided gate electrode (150) located over a substrate (110), the silicided gate electrode (150) having gate sidewall spacers (160) located on sidewalls thereof. The semiconductor device (100) further includes source/drain regions (170) located in the substrate (110) proximate the silicided gate electrode (150), and silicided source/drain regions (180) located in the source/drain regions (170) and at least partially under the gate sidewall spacers (160).
摘要翻译：本发明提供一种半导体器件及其制造方法以及集成电路的制造方法。除了其它可能的元件之外，半导体器件（100）包括位于衬底（110）上方的硅化栅电极（150），硅化栅电极（150）具有位于其侧壁上的栅极侧壁间隔物（160）。半导体器件（100）还包括位于靠近硅化物栅电极（150）的衬底（110）中的源/漏区（170）和位于源/漏区（170）中的硅化源/漏区（180）并且至少部分地在栅极侧壁间隔件（160）下方。

10. 发明授权

US07338888B2 Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same 有权
标题翻译：用于制造具有硅化物栅电极的半导体器件的方法和包括其的集成电路的制造方法
公开(公告)号：US07338888B2
公开(公告)日：2008-03-04
申请号：US10810759
申请日：2004-03-26
申请人： Jiong-Ping Lu , Haowen Bu , Shaofeng Yu , Ping Jiang
发明人： Jiong-Ping Lu , Haowen Bu , Shaofeng Yu , Ping Jiang
IPC分类号： H01L21/28 , H01L21/44 , H01L21/76 , H01L21/4763
CPC分类号： H01L29/66507 , H01L21/28097 , H01L29/4975 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device (100), among other possible steps, includes forming a polysilicon gate electrode over a substrate (110) and forming source/drain regions (170) in the substrate (110) proximate the polysilicon gate electrode. The method further includes forming a blocking layer (180) over the source/drain regions (170), the blocking layer (180) comprising a metal silicide, and siliciding the polysilicon gate electrode to form a silicided gate electrode (150).
摘要翻译：本发明提供一种制造半导体器件的方法及其制造方法，该集成电路包括该半导体器件。除了其他可能的步骤之外，用于制造半导体器件（100）的方法包括在衬底（110）上形成多晶硅栅电极，并在靠近多晶硅栅电极的衬底（110）中形成源/漏区（170）。该方法还包括在源极/漏极区域（170）上形成阻挡层（180），阻挡层（180）包括金属硅化物，并硅化多晶硅栅电极以形成硅化物栅电极（150）。

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