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1. 发明授权

US08665664B2 Semiconductor memory device, memory system including the same, and method for adjusting timing between internal clock and command 有权
标题翻译：半导体存储器件，包括其的存储器系统以及用于调整内部时钟和命令之间的时序的方法
公开(公告)号：US08665664B2
公开(公告)日：2014-03-04
申请号：US12833048
申请日：2010-07-09
申请人： Jinyeong Moon , Sang-Sic Yoon
发明人： Jinyeong Moon , Sang-Sic Yoon
IPC分类号： G11C8/18
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/222 , G11C2207/2254
摘要： A method for adjusting a timing between an internal clock and a command in a gear down mode of a memory device includes detecting a sync pulse at rising and falling edges of the internal clock, and adjusting between the internal clock of the memory device and the command according to the detection result.
摘要翻译：一种用于调整存储器件的减速模式下的内部时钟和命令之间的定时的方法，包括：检测内部时钟的上升沿和下降沿的同步脉冲，以及在存储器件的内部时钟与指令之间进行调整根据检测结果。

2. 发明申请

US20110208883A1 MEMORY DEVICE AND METHOD FOR OPERATING AND CONTROLLING THE SAME 审中-公开
标题翻译：用于操作和控制其的存储器件及其方法
公开(公告)号：US20110208883A1
公开(公告)日：2011-08-25
申请号：US12752660
申请日：2010-04-01
申请人： Jinyeong Moon , Sang-Sic Yoon
发明人： Jinyeong Moon , Sang-Sic Yoon
IPC分类号： G06F13/38 , G06F13/12 , G06F12/00
CPC分类号： G11C7/1006 , G11C7/1009
摘要： A method for operating a memory device includes determining whether or not a data mask operation is to be performed and setting a mask setting value to a predetermined value, receiving a data packet, and extracting mask information from the data packet for masking data in response to the mask information and the mask setting value.
摘要翻译：一种用于操作存储器件的方法包括：确定是否要执行数据掩模操作，并且将掩模设置值设置为预定值，接收数据包，以及响应于所述数据包从屏蔽数据提取屏蔽信息掩码信息和掩码设置值。

3. 发明申请

US20110205818A1 SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD FOR ADJUSTING TIMING BETWEEN INTERNAL CLOCK AND COMMAND 有权
标题翻译：半导体存储器件，包括其的存储器系统和用于调节内部时钟和命令之间的时序的方法
公开(公告)号：US20110205818A1
公开(公告)日：2011-08-25
申请号：US12833048
申请日：2010-07-09
申请人： Jinyeong Moon , Sang-Sic Yoon
发明人： Jinyeong Moon , Sang-Sic Yoon
IPC分类号： G11C8/18 , G11C7/22
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/222 , G11C2207/2254
摘要： A method for adjusting a timing between an internal clock and a command in a gear down mode of a memory device includes detecting a sync pulse at rising and falling edges of the internal clock, and adjusting between the internal clock of the memory device and the command according to the detection result.
摘要翻译：一种用于调整存储器件的减速模式下的内部时钟和命令之间的定时的方法，包括：检测内部时钟的上升沿和下降沿的同步脉冲，以及在存储器件的内部时钟与指令之间进行调整根据检测结果。

4. 发明授权

US08347198B2 Semiconductor memory device having capability of stable initial operation 有权
公开(公告)号：US08347198B2
公开(公告)日：2013-01-01
申请号：US12217064
申请日：2008-06-30
申请人： Beom-Ju Shin , Sang-Sic Yoon
发明人： Beom-Ju Shin , Sang-Sic Yoon
IPC分类号： G06F11/08 , G06F11/30
CPC分类号： G06F11/1004
摘要： A semiconductor memory device is capable of outputting a preset logic level through an EDC pin according to an operation mode during an initial operation, and providing a stable operation according to the specification of the semiconductor memory device just after the input of a data clock (WCK). The semiconductor memory device includes an output circuit configured to output a synchronous data in response to a data clock when the data clock is enabled, and output an asynchronous data when the data clock is disabled, and a data clock detection circuit configured to control outputting the asynchronous data by checking whether the data clock is in a stable state or not.

5. 发明申请

US20090323444A1 SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF 失效
标题翻译：半导体存储器件及其工作方法
公开(公告)号：US20090323444A1
公开(公告)日：2009-12-31
申请号：US12277609
申请日：2008-11-25
申请人： Kyung-Hoon Kim , Sang-Sic Yoon , Bo-Kyeom Kim
发明人： Kyung-Hoon Kim , Sang-Sic Yoon , Bo-Kyeom Kim
IPC分类号： G11C7/22
CPC分类号： G11C7/1051 , G11C7/1048 , G11C7/1057 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C7/225
摘要： A semiconductor memory device including a first clock transmission path configured to receive a source clock swinging at a CML level through a clock transmission line in response to an enable signal, and to convert the source clock into a clock swinging at a CMOS level. The device also includes a second clock transmission path configured to convert the source clock in a clock swinging at a CMOS level in response to the enable signal, and to output the converted clock through the clock transmission line and a data output unit configured to output data in response to output clocks of the first and second clock transmission lines.
摘要翻译：一种半导体存储器件，包括第一时钟传输路径，其被配置为响应于使能信号通过时钟传输线接收在CML电平摆动的源时钟，并将源时钟转换为在CMOS电平摆动的时钟。该装置还包括第二时钟传输路径，其被配置为响应于使能信号在CMOS电平摆动的时钟中转换源时钟，并且经由时钟传输线输出转换的时钟，以及配置为输出数据的数据输出单元响应于第一和第二时钟传输线的输出时钟。

6. 发明申请

US20090222707A1 Semiconductor memory device having capability of stable initial operation 有权
标题翻译：半导体存储器件具有稳定的初始操作能力
公开(公告)号：US20090222707A1
公开(公告)日：2009-09-03
申请号：US12217064
申请日：2008-06-30
申请人： Beom-Ju Shin , Sang-Sic Yoon
发明人： Beom-Ju Shin , Sang-Sic Yoon
IPC分类号： H03M13/09 , G06F11/10 , G06F1/12
CPC分类号： G06F11/1004
摘要： A semiconductor memory device is capable of outputting a preset logic level through an EDC pin according to an operation mode during an initial operation, and providing a stable operation according to the specification of the semiconductor memory device just after the input of a data clock (WCK). The semiconductor memory device includes an output circuit configured to output a synchronous data in response to a data clock when the data clock is enabled, and output an asynchronous data when the data clock is disabled, and a data clock detection circuit configured to control outputting the asynchronous data by checking whether the data clock is in a stable state or not.
摘要翻译：半导体存储器件能够根据初始操作期间的操作模式通过EDC引脚输出预设的逻辑电平，并且在输入数据时钟之后根据半导体存储器件的规格提供稳定的操作（WCK ）。半导体存储器件包括：输出电路，被配置为当数据时钟被使能时，响应于数据时钟输出同步数据，并且当禁止数据时钟时输出异步数据;以及数据时钟检测电路，被配置为控制输出检查异步数据是否处于稳定状态。

7. 发明申请

US20070147149A1 Data output circuit of semiconductor memory apparatus 有权
标题翻译：半导体存储装置的数据输出电路
公开(公告)号：US20070147149A1
公开(公告)日：2007-06-28
申请号：US11592205
申请日：2006-11-03
申请人： Sang-Sic Yoon
发明人： Sang-Sic Yoon
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1069 , G11C29/1201 , G11C29/48 , G11C2207/2227
摘要： A data output circuit of a semiconductor memory apparatus includes: a control unit that outputs a first standby instruction signal, a second standby instruction signal, a first output instruction signal, and a second output instruction signal in response to an input of a standby instruction signal, an output instruction signal, a first test signal, and a second test signal; a first output driver that causes first data to be output or to enter a standby state according to whether or not the first standby instruction signal or the first output instruction signal is enabled; and a second output driver that causes second data to be output or to enter a standby state according to whether or not the second standby instruction signal or the second output instruction signal is enabled.
摘要翻译：半导体存储装置的数据输出电路包括：控制单元，响应于待机指令信号的输入而输出第一待机指令信号，第二待机指令信号，第一输出指令信号和第二输出指令信号，输出指令信号，第一测试信号和第二测试信号; 第一输出驱动器，其根据所述第一备用指令信号还是所述第一输出指令信号是否被使能而使得第一数据被输出或进入待机状态; 以及第二输出驱动器，其根据第二待机指令信号还是第二输出指令信号被使能而使第二数据输出或进入待机状态。

8. 发明授权

US08570097B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08570097B2
公开(公告)日：2013-10-29
申请号：US13411727
申请日：2012-03-05
申请人： Sang-Sic Yoon
发明人： Sang-Sic Yoon
IPC分类号： G05F1/10
CPC分类号： G05F1/56 , G11C5/147
摘要： A semiconductor integrated circuit includes a first pad configured to receive a first voltage, a second pad configured to receive a second voltage, an internal voltage generation circuit configured to generate a third voltage having the same voltage level as the first voltage in response to the second voltage during a test mode, and an internal circuit configured to perform a normal operation using the first voltage and the second voltage during a normal mode and perform a test operation using the second voltage and the third voltage during the test mode.
摘要翻译：半导体集成电路包括：被配置为接收第一电压的第一焊盘，被配置为接收第二电压的第二焊盘;内部电压产生电路，被配置为响应于所述第二电压产生具有与所述第一电压相同的电压电平的第三电压测试模式期间的电压以及在正常模式期间使用第一电压和第二电压进行正常操作的内部电路，并且在测试模式期间使用第二电压和第三电压进行测试操作。

9. 发明授权

US08258840B2 Delay locked loop and integrated circuit including the same 有权
标题翻译：延迟锁定环和集成电路包括相同
公开(公告)号：US08258840B2
公开(公告)日：2012-09-04
申请号：US12980880
申请日：2010-12-29
申请人： Sang-Sic Yoon
发明人： Sang-Sic Yoon
IPC分类号： H03L7/06
CPC分类号： H03L7/0814
摘要： A delay locked loop includes a first delay unit configured to output an output clock by delaying an input clock by a delay; a replica delay unit configured to output a feedback clock by delaying the output clock with a delay equal to a sum of a first delay amount for a first operational frequency of the delayed locked loop and an additional delay amount for a second operational frequency of the delayed locked loop, wherein the second operational frequency is lower than the first operational frequency; and a delay amount control unit configured to control the delay of the first delay unit by comparing a phase of the input clock with a phase of the feedback clock.
摘要翻译：延迟锁定环包括第一延迟单元，其被配置为通过延迟输入时钟来输出输出时钟; 复制延迟单元，被配置为通过延迟等于延迟锁定环路的第一操作频率的第一延迟量和延迟锁定环路的第一操作频率的附加延迟量的延迟来延迟输出时钟来输出反馈时钟，锁定环，其中所述第二操作频率低于所述第一操作频率; 以及延迟量控制单元，被配置为通过将输入时钟的相位与反馈时钟的相位进行比较来控制第一延迟单元的延迟。

10. 发明授权

US07940576B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07940576B2
公开(公告)日：2011-05-10
申请号：US12323687
申请日：2008-11-26
申请人： Bo-Kyeom Kim , Sang-Sic Yoon
发明人： Bo-Kyeom Kim , Sang-Sic Yoon
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/1039 , G11C7/1084 , G11C7/1096 , G11C8/06 , G11C8/12 , G11C11/408 , G11C11/4093 , G11C11/4096
摘要： There is provided a semiconductor memory device, including: a plurality of bank groups each comprising a plurality of banks; a plurality of data pads grouped by a predetermined number for receiving data for the bank groups, wherein the data pads are divided into a plurality of first pad groups receiving data and a plurality of second pad groups selectively receiving data according to a data input/output option value; a first driving unit configured to drive data input via the first pad group to transfer the data input via the first pad group to the bank group corresponding to the first pad group; a second driving unit configured to drive data input via the second pad group to transfer the data input via the second pad group to the bank group corresponding to the second pad group; and a third driving unit configured to drive data input via the first pad group to transfer the data input via the first pad group to the bank group corresponding to the second pad group in response to the data input/output option value.
摘要翻译：提供了一种半导体存储器件，包括：多个银行组，每个组包括多个存储体; 多个用于接收银行组的数据的预定数量的数据焊盘，其中数据焊盘被分成多个接收数据的第一焊盘组和根据数据输入/输出有选择地接收数据的多个第二焊盘组期权价值第一驱动单元，被配置为驱动经由所述第一焊盘组输入的数据，以将经由所述第一焊盘组输入的数据传送到对应于所述第一焊盘组的所述存储体组; 第二驱动单元，被配置为驱动经由所述第二焊盘组输入的数据，以将经由所述第二焊盘组输入的数据传送到对应于所述第二焊盘组的所述存储体组; 以及第三驱动单元，被配置为响应于所述数据输入/输出选项值，经由所述第一焊盘组驱动经由所述第一焊盘组输入的数据到与所述第二焊盘组对应的所述存储体组。

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