专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09000959B2 Turbo encoder apparatus 有权
标题翻译：涡轮编码器装置
公开(公告)号：US09000959B2
公开(公告)日：2015-04-07
申请号：US14370565
申请日：2012-02-24
申请人： Jinsoup Joung , Joohyeong Lee , Jongho Lim , Seungkeun Yook , Ji Hye Shin
发明人： Jinsoup Joung , Joohyeong Lee , Jongho Lim , Seungkeun Yook , Ji Hye Shin
IPC分类号： H03M13/00 , H03M13/47 , H03M13/23 , H03M13/29
CPC分类号： H03M13/47 , H03M13/235 , H03M13/2903 , H03M13/2957 , H03M13/2993 , H03M13/6525 , H03M13/6575
摘要： A turbo encoder apparatus includes: a first element encoder for receiving an input of a bitstream of the data, encoding the input of the bitstream of the data, and generating a first output bitstream in an unit of plural bits; an internal interleaver for generating an interleaved input bitstream from the bitstream of the data; a second element encoder for receiving an input of the interleaved input bitstream in the unit of plural bits, encoding the input of the interleaved input bitstream, and generating a second output bitstream in an unit of plural bits; a trellis-termination-encoder for generating bits for trellis terminations of the first element encoder and the second element encoder; and a bitstream assembler for receiving the first output bitstream, the second output bitstream, and the bits for the trellis terminations and generating an input bitstream for a rate matching.
摘要翻译：涡轮编码器装置包括：第一元件编码器，用于接收数据的比特流的输入，对数据的比特流的输入进行编码，并以多个比特为单位生成第一输出比特流; 内部交织器，用于从所述数据的比特流生成交织的输入比特流; 第二单元编码器，用于以多位为单位接收交织的输入比特流的输入，对交织的输入比特流的输入进行编码，并以多位单位生成第二输出比特流; 网格终端编码器，用于产生用于第一单元编码器和第二单元编码器的网格终端的比特; 以及比特流汇编器，用于接收第一输出比特流，第二输出比特流和用于网格终端的比特，并且生成用于速率匹配的输入比特流。

2. 发明申请

US20140375485A1 TURBO ENCODER APPARATUS 有权
标题翻译：涡轮编码器设备
公开(公告)号：US20140375485A1
公开(公告)日：2014-12-25
申请号：US14370565
申请日：2012-02-24
申请人： Jinsoup Joung , Joohyeong Lee , Jongho Lim , Seungkeun Yook , Ji Hye Shin
发明人： Jinsoup Joung , Joohyeong Lee , Jongho Lim , Seungkeun Yook , Ji Hye Shin
IPC分类号： H03M13/47
CPC分类号： H03M13/47 , H03M13/235 , H03M13/2903 , H03M13/2957 , H03M13/2993 , H03M13/6525 , H03M13/6575
摘要： Disclosed is a turbo encoder apparatus using an improved signal processing method in order to enhance a speed of a turbo encoder used in a channel coding technology. There are effects of reducing a time spent for performing an encoding by performing the encoding in the unit of plural bits every clock cycle and performing a turbo encoding with a structure optimized for a total signal processing processor through the assembly of input forms of encoding output bitstreams in a subsequent signal processing step for encoding through the bitstream assembling apparatus.
摘要翻译：公开了一种使用改进的信号处理方法的turbo编码器装置，以便提高在信道编码技术中使用的turbo编码器的速度。通过以每个时钟周期的多个比特为单位执行编码，并且通过编码输出比特流的输入形式的组合来执行利用针对总信号处理处理器优化的结构的turbo编码来减少执行编码所花费的时间的效果在随后的信号处理步骤中，通过比特流组合装置进行编码。

3. 发明授权

US09344118B2 Apparatus and method for generating interleaver index 有权
标题翻译：用于生成交织器索引的装置和方法
公开(公告)号：US09344118B2
公开(公告)日：2016-05-17
申请号：US14370571
申请日：2012-02-24
申请人： Jinsoup Joung , Joohyeong Lee , Jongho Lim , Jaehwan Kim
发明人： Jinsoup Joung , Joohyeong Lee , Jongho Lim , Jaehwan Kim
IPC分类号： G06F11/00 , H03M13/00 , H03M13/27 , H03M13/39
CPC分类号： H03M13/2771 , H03M13/2739 , H03M13/276 , H03M13/395 , H03M13/6561
摘要： An apparatus for generating indexes of an interleaver for input data comprises: a main processor for calculating an index for a predetermined bit of the input data; and an index operator for receiving the index calculated by the main processor, calculating in parallel indexes for bits after the predetermined bit, and deriving a plurality of indexes. The main processor calculates the index for ith to (i+15)th bits of the input data where i is an integer equal to or larger than 0, and transfers a result of (128*f2)modK to the index operator. The index operator calculates an index for an (i+j+16)th bit where j is an integer which satisfies 0≦j≦7 by using an equation of Π(i+j+16)=(2*Π(i+j+8)−Π(i+j)+128*f2)modK where K is a size of the input data and f2 is a coefficient calculated from K.
摘要翻译：一种用于产生用于输入数据的交织器的索引的装置，包括：主处理器，用于计算输入数据的预定位的索引; 以及索引运算器，用于接收由主处理器计算的索引，在预定比特之后对比特的并行索引计算，并导出多个索引。主处理器计算输入数据的第i至第（i + 15）位的索引，其中i是等于或大于0的整数，并将（128 * f2）modK的结果传送给索引操作符。索引算子通过使用＆Pgr;（i + j + 16）=（2 *＆Pgr;（i + j + 16）的等式来计算第（i + j + 16）位的索引，其中j是满足0＆nlE; j＆ i + j + 8） - ＆Pgr;（i + j）+ 128 * f2）modK其中K是输入数据的大小，f2是从K计算的系数。

4. 发明申请

US20150026535A1 APPARATUS AND METHOD FOR GENERATING INTERLEAVER INDEX 有权
标题翻译：用于生成交换索引的装置和方法
公开(公告)号：US20150026535A1
公开(公告)日：2015-01-22
申请号：US14370571
申请日：2012-02-24
申请人： Jinsoup Joung , Joohyeong Lee , Jongho Lim , Jaehwan Kim
发明人： Jinsoup Joung , Joohyeong Lee , Jongho Lim , Jaehwan Kim
IPC分类号： H03M13/27
CPC分类号： H03M13/2771 , H03M13/2739 , H03M13/276 , H03M13/395 , H03M13/6561
摘要： Disclosed is an apparatus and a method for generating an internal interleaver index of a turbo encoder in parallel. There are effects of reducing the time spent for generating total indexes by generating indexes for a plurality of bits in parallel and improving the resource efficiency and the performance in the hardware implementation by calculating indexes for following bits through the use of an index calculated for a predetermined bit without the use of a multiplier and a divider.
摘要翻译：公开了并行地生成turbo编码器的内部交织器索引的装置和方法。通过使用针对预定的方式计算的索引来计算跟踪比特的索引，具有减少用于并行生成多个比特的索引并且提高资源效率和硬件实现中的性能来生成总索引的时间的效果位而不使用乘法器和分频器。

5. 发明申请

US20130187694A1 DIGITAL RE-SAMPLING APPARATUS USING FRACTIONAL DELAY GENERATOR 有权
标题翻译：数字再采样器采用分时延迟发生器
公开(公告)号：US20130187694A1
公开(公告)日：2013-07-25
申请号：US13816255
申请日：2010-12-30
申请人： Jinsoup Joung , Kyeongmin Ha , Joohyeong Lee
发明人： Jinsoup Joung , Kyeongmin Ha , Joohyeong Lee
IPC分类号： H03H17/04
CPC分类号： H03H17/0444 , H03H17/0027 , H03H17/0642
摘要： Disclosed herein is a digital re-sampling apparatus. The digital re-sampling apparatus includes a sample buffer, a sample buffer control unit, a filter bank, a first delay bank, a fractional delay constant table, a combiner bank, and a second delay bank. The sample buffer temporarily stores an input sample in synchronization with an input sampling frequency. The sample buffer control unit controls writing and reading operations. The filter bank includes a number of digital filters equal to the number of stages, and filters the input sample. The first delay bank differentially delays a filter output value. The fractional delay constant table stores information about re-sampling time. The combiner bank includes a number of adders and multipliers, performs an operation, and outputs a re-sampled value. The second delay bank causes a delay so that output of each combiner can be synchronized with each output of the fractional delay constant table.
摘要翻译：这里公开了一种数字再采样装置。数字重采样装置包括采样缓冲器，采样缓冲器控制单元，滤波器组，第一延迟组，分数延迟常数表，组合器组和第二延迟组。采样缓冲器与输入采样频率同步地临时存储输入采样。采样缓冲器控制单元控制写入和读取操作。滤波器组包括等于级数的多个数字滤波器，并对输入样本进行滤波。第一个延迟组差分地延迟滤波器输出值。分数延迟常数表存储关于重新采样时间的信息。组合器组包括多个加法器和乘法器，执行操作，并且输出重新采样的值。第二延迟组引起延迟，使得每个组合器的输出可以与分数延迟常数表的每个输出同步。

6. 发明授权

US08787513B2 Digital re-sampling apparatus using fractional delay generator 有权
$Digital re-sampling apparatus using fractional delay generator$
标题翻译：使用分数延迟发生器的数字再采样装置
公开(公告)号：US08787513B2
公开(公告)日：2014-07-22
申请号：US13816255
申请日：2010-12-30
申请人： Jinsoup Joung , Kyeongmin Ha , Joohyeong Lee
发明人： Jinsoup Joung , Kyeongmin Ha , Joohyeong Lee
IPC分类号： H04L7/00 , H03H17/06 , H03H17/04 , H03H17/00
CPC分类号： H03H17/0444 , H03H17/0027 , H03H17/0642
摘要： Disclosed herein is a digital re-sampling apparatus. The digital re-sampling apparatus includes a sample buffer, a sample buffer control unit, a filter bank, a first delay bank, a fractional delay constant table, a combiner bank, and a second delay bank. The sample buffer temporarily stores an input sample in synchronization with an input sampling frequency. The sample buffer control unit controls writing and reading operations. The filter bank includes a number of digital filters equal to the number of stages, and filters the input sample. The first delay bank differentially delays a filter output value. The fractional delay constant table stores information about re-sampling time. The combiner bank includes a number of adders and multipliers, performs an operation, and outputs a re-sampled value. The second delay bank causes a delay so that output of each combiner can be synchronized with each output of the fractional delay constant table.
摘要翻译：这里公开了一种数字再采样装置。数字重采样装置包括采样缓冲器，采样缓冲器控制单元，滤波器组，第一延迟组，分数延迟常数表，组合器组和第二延迟组。采样缓冲器与输入采样频率同步地临时存储输入采样。采样缓冲器控制单元控制写入和读取操作。滤波器组包括等于级数的多个数字滤波器，并对输入样本进行滤波。第一个延迟组差分地延迟滤波器输出值。分数延迟常数表存储关于重新采样时间的信息。组合器组包括多个加法器和乘法器，执行操作，并且输出重新采样的值。第二延迟组引起延迟，使得每个组合器的输出可以与分数延迟常数表的每个输出同步。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式