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1. 发明授权

US06278964B1 Hot carrier effect simulation for integrated circuits 失效
标题翻译：集成电路的热载体效应仿真
公开(公告)号：US06278964B1
公开(公告)日：2001-08-21
申请号：US09087413
申请日：1998-05-29
申请人： Jingkun Fang , Hirokazu Yonezawa , Lifeng Wu , Yoshiyuki Kawakami , Nobufusa Iwanishi , Alvin I-Hsien Chen , Norio Koike , Ping Chen , Chune-Sin Yeh , Zhihong Liu
发明人： Jingkun Fang , Hirokazu Yonezawa , Lifeng Wu , Yoshiyuki Kawakami , Nobufusa Iwanishi , Alvin I-Hsien Chen , Norio Koike , Ping Chen , Chune-Sin Yeh , Zhihong Liu
IPC分类号： G06F1126
CPC分类号： G01R31/318357 , G01R31/318328 , G06F17/5022
摘要： An approach for simulating hot carrier effects in an integrated circuit (IC) at the circuit level includes generating a hot carrier library of delay data for each cell in the IC, using the hot carrier library data to generate a set of scaled timing data for the IC and using the scaled timing data with a IC performance simulator to simulate the IC operation. The scaled timing data is based upon the cell delay data and time-based switching activity of each cell in the IC.
摘要翻译：用于在电路级模拟集成电路（IC）中的热载流子效应的方法包括使用热载体库数据产生一组缩放的定时数据，以生成针对IC卡中的每个单元的延迟数据的热载体库 IC，并使用IC性能仿真器对缩放的时序数据进行模拟，以模拟IC的工作。缩放的定时数据基于IC中每个单元的单元延迟数据和基于时间的切换活动。

2. 发明授权

US06795802B2 Apparatus and method for calculating temporal deterioration margin amount of LSI, and LSI inspection method 失效
标题翻译：用于计算LSI的时间恶化裕量的装置和方法，以及LSI检查方法
公开(公告)号：US06795802B2
公开(公告)日：2004-09-21
申请号：US09810518
申请日：2001-03-19
申请人： Hirokazu Yonezawa , Yoshiyuki Kawakami , Nobufusa Iwanishi
发明人： Hirokazu Yonezawa , Yoshiyuki Kawakami , Nobufusa Iwanishi
IPC分类号： G06F1710
CPC分类号： G01R31/318371 , G01R31/287 , G01R31/318342
摘要： The present invention makes it possible to obtain an aging deterioration margin amount including an allowance for aging deterioration in a simplified manner. Moreover, in order to allow an appropriate inspection taking aging deterioration into account, a delay deterioration rate predicting part 101 outputs signal path delay information before deterioration 302 and signal path delay deterioration rate information 303 for each signal path, based on LSI design information 301. A delay vs. delay deterioration rate analyzing part 102 outputs delay vs. delay deterioration rate relationship information 304 showing the correlation between the delay and the delay deterioration rate based on the information. A delay deterioration rate extracting part 103 extracts a delay deterioration rate of a predetermined signal path and outputs it as delay deterioration margin 305. A delay deterioration margin amount calculating part 104 calculates a delay deterioration margin amount by using the delay deterioration margin 305 as a derating factor G. Furthermore, a inspection operation frequency calculating part 105 calculates an operation frequency for inspection using the delay deterioration margin 305 as a derating factor G.
摘要翻译：本发明使得可以简化地获得包括老化劣化余地的老化退化裕度量。此外，为了考虑老化劣化的适当检查，延迟劣化率预测部101基于LSI设计信息301，对各信号路径输出恶化前的信号路径延迟信息302和信号路径延迟劣化率信息303。延迟与延迟劣化率分析部分102基于该信息输出延迟与延迟退化率关系信息304，其显示延迟和延迟退化率之间的相关性。延迟劣化率提取部分103提取预定信号路径的延迟劣化率，并将其作为延迟劣化边缘305输出。延迟劣化边际量计算部分104通过使用延迟劣化边缘305作为降额来计算延迟劣化边际量另外，检查动作频率计算部105使用延迟劣化余量305作为降额因子G来计算检查用的操作频率。

3. 发明授权

US07222319B2 Timing analysis method and apparatus 有权
标题翻译：时序分析方法和装置
公开(公告)号：US07222319B2
公开(公告)日：2007-05-22
申请号：US11101572
申请日：2005-04-08
申请人： Hirokazu Yonezawa
发明人： Hirokazu Yonezawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A timing analysis apparatus reads a net list including connection information and the like of circuit cells of an LSI, delay data for previously storing delay information of the circuit cells, stage count-derating factor dependency and components P, V and T of a derating factor; detects the number of stages of each signal path by a signal path cell counting section; determines a derating factor corresponding to the extent of averaging of random variation of each signal path in accordance with the number of stages of the signal path; and performs timing analysis on the basis of the determined derating factor. Therefore, more realistic and highly accurate timing design can be performed on a large-scale circuit.
摘要翻译：定时分析装置读取包括LSI的电路单元的连接信息等的网络列表，用于预先存储电路单元的延迟信息的延迟数据，级数降额因子依赖性和降额因子的分量P，V和T ; 通过信号路径单元计数部检测各信号路径的级数; 根据信号路径的级数确定与每个信号路径的随机变化的平均程度相对应的降额因子; 并根据确定的降额因子进行定时分析。因此，可以在大规模电路上执行更实际和高度精确的定时设计。

4. 发明申请

US20050177356A1 Circuit simulation method and circuit simulation apparatus 审中-公开
标题翻译：电路仿真方法及电路仿真装置
公开(公告)号：US20050177356A1
公开(公告)日：2005-08-11
申请号：US10979226
申请日：2004-11-03
申请人： Hirokazu Yonezawa
发明人： Hirokazu Yonezawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Variables corresponding to a plurality of fabrication variation components per parameter out of parameters included in input information are incorporated in accordance with a given model. Fabrication variation of the parameter is obtained by selectively giving fabrication variation information of respective fabrication variation components to the variables corresponding to the plurality of fabrication variation components by using the model, and input information influenced by the fabrication variation is output. In accordance with the output, circuit simulation is executed by referring to the input information influenced by the fabrication variation of the parameter.
摘要翻译：根据给定的模型来合并对应于输入信息中包括的参数中的每个参数的多个制造变化分量的变量。通过使用该模型，通过选择性地将各个制造变化分量的制造变化信息提供给对应于多个制造变化分量的变量来获得参数的制造变化，并且输出受制造变化影响的输入信息。根据输出，通过参考受参数制造变化影响的输入信息来执行电路仿真。

5. 发明授权

US07308381B2 Timing verification method for semiconductor integrated circuit 有权
公开(公告)号：US07308381B2
公开(公告)日：2007-12-11
申请号：US11495778
申请日：2006-07-31
申请人： Hirokazu Yonezawa
发明人： Hirokazu Yonezawa
IPC分类号： G06F1/12
CPC分类号： G06F17/5022
摘要： Initially, non-uniformity of statistical skews between a plurality of clock output terminal pairs is calculated. Next, a partial circuit driven by a clock output terminal pair having each skew distribution is extracted from an integrated circuit. Next, a second statistical timing characteristic which is a maximum value in the partial circuit is obtained from a first statistical timing characteristic of signal paths included in the extracted partial circuit. Next, timing verification for the integrated circuit is performed using the second statistical timing characteristics corresponding to the respective statistical clock skews.

6. 发明授权

US07239997B2 Apparatus for statistical LSI delay simulation 失效
标题翻译：统计LSI延迟模拟装置
公开(公告)号：US07239997B2
公开(公告)日：2007-07-03
申请号：US10756471
申请日：2004-01-14
申请人： Hirokazu Yonezawa
发明人： Hirokazu Yonezawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036 , G06F2217/10
摘要： A statistical delay simulation apparatus includes: a circuit simulator for simulating a circuit operation of a circuit cell constituting an LSI; a statistical delay library generator for driving the circuit simulator and generating, based on a process parameter and the like, a statistical delay library in which the dependency of a delay variation on a predetermined operation condition in each circuit cell is described; a delay calculator for calculating a delay amount of each circuit cell to generate a statistical LSI delay information file containing data on the calculated delay amount; and a static timing analyzer for simulating, based on data of the statistical LSI delay information file, an operation with a delay variation of the LSI to generate a statistical LSI delay analysis result file.
摘要翻译：一种统计延迟模拟装置，包括：模拟构成LSI的电路单元的电路动作的电路模拟器; 用于驱动电路仿真器的统计延迟库发生器，并且基于处理参数等产生描述延迟变化对每个电路单元中的预定操作条件的依赖性的统计延迟库; 延迟计算器，用于计算每个电路单元的延迟量以产生包含关于所计算的延迟量的数据的统计LSI延迟信息文件; 以及静态定时分析器，用于基于统计LSI延迟信息文件的数据模拟具有LSI的延迟变化的操作，以生成统计LSI延迟分析结果文件。

7. 发明授权

US5475825A Semiconductor device having combined fully associative memories 失效
标题翻译：具有组合的完全关联存储器的半导体器件
公开(公告)号：US5475825A
公开(公告)日：1995-12-12
申请号：US952990
申请日：1992-09-29
申请人： Hirokazu Yonezawa , Seiji Yamaguchi
发明人： Hirokazu Yonezawa , Seiji Yamaguchi
IPC分类号： G06F12/10 , G11C11/00 , G11C15/04 , H01L27/10 , G06F13/00 , G11C15/00
CPC分类号： G06F12/1054 , G11C11/005 , G11C15/04
摘要： As a TLB (translation look-aside buffer) of a fully associative system is organized, a first CAM (content addressable memory) cell array and a first RAM (random access memory) cell array which together make up one entry are arranged in such a way that they face each other across a control circuit. As a cache memory of a fully associative system is organized, a second CAM cell array and a second RAM cell array which together make up one entry are arranged in such a way that they face each other across the control circuit. Additionally, the second CAM cell array is located next to the first RAM cell array, whereas the second RAM cell array is located next to the first CAM cell array. These four cell arrays make up one section. At the time of a hit in the first CAM cell array, the control circuit enables readout of the first RAM cell array, while it, at the time of a hit of the second CAM cell array, enables readout of the second RAM cell array. Based on logical addresses issued to the first CAM cell array, physical addresses are read from the first RAM cell array. Such physical addresses are supplied to the second CAM cell array as tags for the readout of data from the second RAM cell array.
摘要翻译：作为完全关联系统的TLB（翻译后备缓冲器），组织了一起组合一个条目的第一CAM（内容可寻址存储器）单元阵列和第一RAM（随机存取存储器）单元阵列，他们在控制电路上面对面的方式。作为完全关联系统的高速缓冲存储器被组织，一起构成一个条目的第二CAM单元阵列和第二RAM单元阵列被布置成使得它们跨越控制电路相互面对。此外，第二CAM单元阵列位于第一RAM单元阵列旁边，而第二RAM单元阵列位于第一CAM单元阵列旁边。这四个单元阵列组成一个部分。在第一CAM单元阵列中的命中时，控制电路能够读出第一RAM单元阵列，而在第二CAM单元阵列的命中时它能够读出第二RAM单元阵列。基于发给第一CAM单元阵列的逻辑地址，从第一RAM单元阵列读取物理地址。这样的物理地址被提供给第二CAM单元阵列作为用于从第二RAM单元阵列读出数据的标签。

8. 发明申请

US20060107244A1 Method for designing semiconductor intgrated circuit and system for designing the same 审中-公开
标题翻译：设计半导体集成电路的方法及其设计系统
公开(公告)号：US20060107244A1
公开(公告)日：2006-05-18
申请号：US11208741
申请日：2005-08-23
申请人： Hirokazu Yonezawa
发明人： Hirokazu Yonezawa
IPC分类号： G06F17/50 , G06F9/45 , G06G7/62
CPC分类号： G06F17/5022 , G06F17/5045
摘要： A total random number sequence generator generates a total random number sequence of an entire circuit, as fabrication variation. A signal path random number sequence extracting section extracts, from the total random number sequence, a signal path random number sequence for a partial circuit obtained by dividing the entire circuit. A circuit simulating section executes Monte Carlo analysis using the signal path random number sequence for each partial circuit, thereby obtaining a desired circuit characteristic distribution. In this manner, correlation is maintained between divided circuit characteristic distributions and, in addition, the obtained circuit characteristic distribution is used for clock skew distribution calculation and others. Moreover, the circuit scale of a target of circuit simulation is reduced.
摘要翻译：总随机数序列发生器产生整个电路的总随机数序列作为制造变化。信号路径随机数序列提取部分从总随机数序列中提取通过划分整个电路获得的部分电路的信号路径随机数序列。电路模拟部分使用每个部分电路的信号路径随机数序列执行蒙特卡洛分析，从而获得期望的电路特性分布。以这种方式，在分割电路特性分布之间保持相关性，并且所获得的电路特性分布用于时钟偏差分布计算等。此外，减少了电路仿真目标的电路规模。

9. 发明授权

US5463751A Memory device having address translator and comparator for comparing memory cell array outputs 失效
标题翻译：具有用于比较存储单元阵列输出的地址转换器和比较器的存储器件
公开(公告)号：US5463751A
公开(公告)日：1995-10-31
申请号：US358688
申请日：1994-12-19
申请人： Hirokazu Yonezawa , Seiji Yamaguchi
发明人： Hirokazu Yonezawa , Seiji Yamaguchi
IPC分类号： G06F12/10
CPC分类号： G06F12/1027
摘要： A semiconductor memory device has an address translator and a comparator. An entry of the address translator includes an associative memory cell array for storing and comparing a logical address of at least m bits. A first decoder generates a first word signal for the associative memory cell array. A first random access memory cell array stores a physical address of m bits. A controller generates a word signal for the first random access memory cell according to the first word signal and a result of a comparison by the associative memory cell array. A second random access memory cell stores a physical address of m bits. The second random access memory cell is physically disposed near the first random access memory cell array. A second decoder generates a second word signal for the second random access memory cell array. Outputs of the first and second random access memory cell arrays are connected to and compared by the comparator which outputs a signal upon coincidence between the outputs of the first and second random access memory cell arrays.
摘要翻译：半导体存储器件具有地址转换器和比较器。地址转换器的条目包括用于存储和比较至少m位的逻辑地址的关联存储单元阵列。第一解码器产生关联存储单元阵列的第一字信号。第一随机存取存储单元阵列存储m位的物理地址。控制器根据第一字信号产生用于第一随机存取存储器单元的字信号和由关联存储单元阵列的比较结果。第二随机存取存储器单元存储m位的物理地址。第二随机存取存储器单元物理地布置在第一随机存取存储单元阵列附近。第二解码器产生用于第二随机存取存储单元阵列的第二字信号。第一和第二随机存取存储单元阵列的输出连接到比较器，比较器在第一和第二随机存取存储单元阵列的输出之间一致地输出信号。

10. 发明授权

US07197728B2 Method for setting design margin for LSI 有权
标题翻译：设置LSI设计余量的方法
公开(公告)号：US07197728B2
公开(公告)日：2007-03-27
申请号：US10868832
申请日：2004-06-17
申请人： Hirokazu Yonezawa
发明人： Hirokazu Yonezawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： After predicting a relationship between a design margin set against a fabrication variation in design of an LSI and a yield, a specific design margin for attaining a given yield is calculated based on the predicated relationship. The yield is a delay yield obtained by cumulating a signal propagation delay time thereby achieving a probability that a signal propagated through a logic circuit of the LSI is delayed by a given amount of time, and the design margin is a derating factor indicating a ratio between the signal propagation delay time and a standard value of the signal propagation delay time.
摘要翻译：在预测设计裕度设置与LSI的设计制造变化和产量之间的关系之后，基于所预测的关系来计算用于获得给定产量的特定设计余量。产量是通过累加信号传播延迟时间而获得的延迟收益，从而实现通过LSI的逻辑电路传播的信号延迟给定时间量的概率，并且设计余量是指示降低系数信号传播延迟时间和信号传播延迟时间的标准值。

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