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1. 发明授权

US08004328B2 AC-coupling phase interpolator and delay-locked loop using the same 失效
标题翻译：交流耦合相位内插器和使用其的延迟锁定环路
公开(公告)号：US08004328B2
公开(公告)日：2011-08-23
申请号：US12570186
申请日：2009-09-30
申请人： Jin-Gook Kim , Kwang-II Park , Seung-Jun Bae , Si-Hong Kim , Dae-Hyun Chung
发明人： Jin-Gook Kim , Kwang-II Park , Seung-Jun Bae , Si-Hong Kim , Dae-Hyun Chung
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03K5/13 , H03K2005/00052 , H03L7/0814
摘要： An AC-coupling phase interpolator and a DLL using the same are provided. The AC-coupling phase interpolator includes a coupling capacitor generating and outputting a coupling signal by AC-coupling to an interpolation signal obtained by phase-interpolating an input signal. Thereby, it is possible to correct duty of an input signal and adjust the level of an output signal.
摘要翻译：提供AC耦合相位内插器和使用它的DLL。 AC耦合相位内插器包括耦合电容器，其通过AC耦合产生并输出耦合信号，所述耦合信号通过对输入信号进行相位插值而获得。由此，可以校正输入信号的占空比并调整输出信号的电平。

2. 发明授权

US07737748B2 Level shifter of semiconductor device and method for controlling duty ratio in the device 有权
标题翻译：半导体器件的电平移位器和装置中占空比的控制方法
公开(公告)号：US07737748B2
公开(公告)日：2010-06-15
申请号：US11986841
申请日：2007-11-27
申请人： Jin-Gook Kim , Seung-Jun Bae , Dae-Hyun Chung
发明人： Jin-Gook Kim , Seung-Jun Bae , Dae-Hyun Chung
IPC分类号： H03K3/017
CPC分类号： H03K3/35613 , H03K3/017
摘要： A level shifter of a semiconductor device and method of controlling a duty ratio are provided. The level shifter includes first and second PMOS transistors having sources to which a power supply voltage is applied, first and second NMOS transistors having sources to which a ground voltage is applied, third and fourth NMOS transistors having sources connected to drains of the first and second NMOS transistors and gates to which the power supply voltage is applied; and a voltage controlled delay unit for receiving an input signal applied to a gate of the first NMOS transistor, inverting a level of the input signal, determining whether a voltage of an inverted input signal should be charged in response to a voltage control signal, outputting the voltage of the inverted input signal of which delay time is controlled, and applying the inverted input signal to a gate of the second NMOS transistor.
摘要翻译：提供半导体器件的电平移位器和控制占空比的方法。电平移位器包括具有施加电源电压的源的第一和第二PMOS晶体管，具有施加接地电压的源的第一和第二NMOS晶体管，具有连接到第一和第二漏极的漏极的源的第三和第四NMOS晶体管施加电源电压的NMOS晶体管和栅极; 以及电压控制延迟单元，用于接收施加到第一NMOS晶体管的栅极的输入信号，反相输入信号的电平，确定反相输入信号的电压是否应当响应于电压控制信号而被充电，输出控制延迟时间的反相输入信号的电压，并将反相输入信号施加到第二NMOS晶体管的栅极。

3. 发明申请

US20080186075A1 Level shifter of semiconductor device and method for controlling duty ratio in the device 有权
标题翻译：半导体器件的电平移位器和装置中占空比的控制方法
公开(公告)号：US20080186075A1
公开(公告)日：2008-08-07
申请号：US11986841
申请日：2007-11-27
申请人： Jin-Gook Kim , Seung-Jun Bae , Dae-Hyun Chung
发明人： Jin-Gook Kim , Seung-Jun Bae , Dae-Hyun Chung
IPC分类号： H03L5/00
CPC分类号： H03K3/35613 , H03K3/017
摘要： A level shifter of a semiconductor device and method of controlling a duty ratio are provided. The level shifter includes first and second PMOS transistors having sources to which a power supply voltage is applied, first and second NMOS transistors having sources to which a ground voltage is applied, third and fourth NMOS transistors having sources connected to drains of the first and second NMOS transistors and gates to which the power supply voltage is applied; and a voltage controlled delay unit for receiving an input signal applied to a gate of the first NMOS transistor, inverting a level of the input signal, determining whether a voltage of an inverted input signal should be charged in response to a voltage control signal, outputting the voltage of the inverted input signal of which delay time is controlled, and applying the inverted input signal to a gate of the second NMOS transistor.
摘要翻译：提供半导体器件的电平移位器和控制占空比的方法。电平移位器包括具有施加电源电压的源的第一和第二PMOS晶体管，具有施加接地电压的源的第一和第二NMOS晶体管，具有连接到第一和第二漏极的漏极的源的第三和第四NMOS晶体管施加电源电压的NMOS晶体管和栅极; 以及电压控制延迟单元，用于接收施加到第一NMOS晶体管的栅极的输入信号，反相输入信号的电平，确定反相输入信号的电压是否应当响应于电压控制信号而被充电，输出控制延迟时间的反相输入信号的电压，并将反相输入信号施加到第二NMOS晶体管的栅极。

4. 发明申请

US20070194968A1 MEMORY SYSTEM INCLUDING A POWER DIVIDER ON A MULTI MODULE MEMORY BUS 有权
标题翻译：在多模块存储器总线上包括功率分配器的存储器系统
公开(公告)号：US20070194968A1
公开(公告)日：2007-08-23
申请号：US11668397
申请日：2007-01-29
申请人： Myung-Hee Sung , Jin-Gook Kim , Joung-Ho Kim , Jong-Hoon Kim
发明人： Myung-Hee Sung , Jin-Gook Kim , Joung-Ho Kim , Jong-Hoon Kim
IPC分类号： H03M1/78
CPC分类号： G11C5/063 , G11C5/04 , G11C5/14
摘要： A memory system includes a memory controller, a transmission bus, a power divider, a first memory chip, and a second memory chip. The transmission bus is coupled from the memory controller to a first node of the power divider for transferring signals. The first node of the power divider is coupled to a second node of the power divider via a first line, and the first node is also coupled to a third node of the power divider via a second line. The first memory chip is coupled to the second node via a first branch bus and the second memory chip is coupled to the third node via a second branch bus. Accordingly, reflected wave due to an impedance mismatching can be reduced to enhance the signal integrity.
摘要翻译：存储器系统包括存储器控制器，传输总线，功率分配器，第一存储器芯片和第二存储器芯片。传输总线从存储器控制器耦合到功率分配器的第一节点，用于传送信号。功率分配器的第一节点通过第一线耦合到功率分配器的第二节点，并且第一节点也经由第二线路耦合到功率分配器的第三节点。第一存储器芯片经由第一分支总线耦合到第二节点，并且第二存储器芯片经由第二分支总线耦合到第三节点。因此，可以减少由于阻抗不匹配引起的反射波，以增强信号完整性。

5. 发明授权

US07772915B2 Temperature sensing circuit and method using DLL 有权
标题翻译：温度感应电路及其使用方法
公开(公告)号：US07772915B2
公开(公告)日：2010-08-10
申请号：US12130117
申请日：2008-05-30
申请人： Jin-Gook Kim
发明人： Jin-Gook Kim
IPC分类号： H01L35/00 , G01K7/00
CPC分类号： H03K5/133 , G01K7/01 , G11C7/04 , G11C11/406 , G11C11/40626 , H03K2005/00039 , H03L7/0814
摘要： A temperature sensing circuit using a delay locked loop and a temperature sensing method. The temperature sensing circuit includes a locked delay unit for receiving an external clock and generating a locked delay pulse keeping a constant delay amount regardless of temperature. A variable delay unit may have a chain structure of a plurality of delay cells depending upon temperature. The variable delay unit may receive the external clock and generate variable delay pulses having respectively different delay amounts based on temperature. A decision control unit is configured to sense a determination temperature by using a phase difference between one selected from the variable delay pulses and the locked delay pulse. Accordingly, an unnecessary time and cost causable by temperature compensation can be reduced, and an automatic temperature compensation and a precise temperature sensing operation can be obtained.
摘要翻译：使用延迟锁定环路的温度检测电路和温度检测方法。温度检测电路包括锁定延迟单元，用于接收外部时钟并产生锁定的延迟脉冲，保持恒定的延迟量而不管温度如何。可变延迟单元可以具有取决于温度的多个延迟单元的链结构。可变延迟单元可以接收外部时钟并产生基于温度分别具有不同延迟量的可变延迟脉冲。判定控制单元被配置为通过使用从可变延迟脉冲和锁定延迟脉冲之间选择的一个之间的相位差来感测确定温度。因此，可以降低由温度补偿导致的不必要的时间和成本，并且可以获得自动温度补偿和精确的温度感测操作。

6. 发明授权

US07646212B2 Memory system including a power divider on a multi module memory bus 有权
标题翻译：存储系统包括多模块存储器总线上的功率分配器
公开(公告)号：US07646212B2
公开(公告)日：2010-01-12
申请号：US11668397
申请日：2007-01-29
申请人： Myung-Hee Sung , Jin-Gook Kim , Joung-Ho Kim , Jong-Hoon Kim
发明人： Myung-Hee Sung , Jin-Gook Kim , Joung-Ho Kim , Jong-Hoon Kim
IPC分类号： H03K19/003
CPC分类号： G11C5/063 , G11C5/04 , G11C5/14
摘要： A memory system includes a memory controller, a transmission bus, a power divider, a first memory chip, and a second memory chip. The transmission bus is coupled from the memory controller to a first node of the power divider for transferring signals. The first node of the power divider is coupled to a second node of the power divider via a first line, and the first node is also coupled to a third node of the power divider via a second line. The first memory chip is coupled to the second node via a first branch bus and the second memory chip is coupled to the third node via a second branch bus. Accordingly, reflected wave due to an impedance mismatching can be reduced to enhance the signal integrity.
摘要翻译：存储器系统包括存储器控制器，传输总线，功率分配器，第一存储器芯片和第二存储器芯片。传输总线从存储器控制器耦合到功率分配器的第一节点，用于传送信号。功率分配器的第一节点通过第一线耦合到功率分配器的第二节点，并且第一节点也经由第二线路耦合到功率分配器的第三节点。第一存储器芯片经由第一分支总线耦合到第二节点，并且第二存储器芯片经由第二分支总线耦合到第三节点。因此，可以减少由于阻抗不匹配引起的反射波，以增强信号完整性。

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