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1. 发明授权

US07751252B2 Semiconductor memory with a reference current generating circuit having a reference current generating section and an amplifier section 有权
标题翻译：具有参考电流产生电路的半导体存储器，具有参考电流产生部分和放大器部分
公开(公告)号：US07751252B2
公开(公告)日：2010-07-06
申请号：US12273979
申请日：2008-11-19
申请人： Jin Kashiwagi , Yasuhiko Honda , Yoshihiko Kamata
发明人： Jin Kashiwagi , Yasuhiko Honda , Yoshihiko Kamata
IPC分类号： G11C16/28
CPC分类号： G11C7/14 , G11C16/28
摘要： A semiconductor memory capable of storing and reading data in a memory cell for holding the data corresponding to a threshold voltage has a reference current generating circuit having a reference current generating section and an amplifier section.
摘要翻译：能够存储和读取存储单元中用于保持对应于阈值电压的数据的数据的半导体存储器具有参考电流产生电路，其具有参考电流产生部分和放大器部分。

2. 发明申请

US20100238736A1 Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：US20100238736A1
公开(公告)日：2010-09-23
申请号：US12659092
申请日：2010-02-25
申请人： Yoshihiko Kamata , Jin Kashiwagi , Hikaru Mochizuki
发明人： Yoshihiko Kamata , Jin Kashiwagi , Hikaru Mochizuki
IPC分类号： G11C16/06 , G11C5/14 , G11C7/06
CPC分类号： G11C11/5628 , G11C16/3436
摘要： 1. A semiconductor storage device has a first MOS transistor connected at a first end thereof to a power supply and diode-connected; a second MOS transistor connected in parallel with the first MOS transistor; a memory cell connected between the second end of the first MOS transistor and ground, the memory cell capable of adjusting a current flowing through the memory cell; a third MOS transistor connected at a first end thereof to the power supply, and diode-connected; a fourth MOS transistor connected in parallel with the third MOS transistor; a fifth MOS transistor connected between the second end of the fourth MOS transistor and the ground and supplied at a gate thereof with the first reference voltage; and an amplifier circuit which compares the sense voltage with the comparison voltage, and which outputs a comparison result signal depending upon a result of the comparison.
摘要翻译：半导体存储装置的第一MOS晶体管的第一端与电源连接，二极管连接; 与第一MOS晶体管并联连接的第二MOS晶体管; 连接在第一MOS晶体管的第二端和地之间的存储单元，所述存储单元能够调节流过所述存储单元的电流; 第三MOS晶体管，其第一端连接到电源，二极管连接; 与第三MOS晶体管并联连接的第四MOS晶体管; 连接在第四MOS晶体管的第二端和地之间并在其栅极处提供第一参考电压的第五MOS晶体管; 以及放大器电路，其将感测电压与比较电压进行比较，并且根据比较结果输出比较结果信号。

3. 发明授权

US07466610B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07466610B2
公开(公告)日：2008-12-16
申请号：US11690420
申请日：2007-03-23
申请人： Akira Umezawa , Jin Kashiwagi
发明人： Akira Umezawa , Jin Kashiwagi
IPC分类号： G11C11/00
CPC分类号： G11C16/26 , G11C16/04 , G11C29/021 , G11C29/028 , G11C29/24
摘要： A non-volatile semiconductor memory device comprises a redundant memory cell to store address data of a defect cell in a memory cell array. A first decoder circuit is given a first drive voltage to provide a control signal to the redundant memory cell. A dummy memory cell has a threshold voltage corresponding to the redundant memory cell. A second decoder circuit is given a second drive voltage corresponding to the first drive voltage to provide a control signal to the dummy memory cell. A comparator circuit compares data to be read out of the dummy memory cell with data actually read out of the dummy memory cell.
摘要翻译：非易失性半导体存储器件包括用于存储存储单元阵列中的缺陷单元的地址数据的冗余存储单元。第一解码器电路被给予第一驱动电压以向冗余存储器单元提供控制信号。虚拟存储单元具有对应于冗余存储单元的阈值电压。第二解码器电路被给予对应于第一驱动电压的第二驱动电压，以向虚拟存储器单元提供控制信号。比较器电路将要从虚拟存储器单元读出的数据与从虚拟存储单元实际读出的数据进行比较。

4. 发明申请

US20120134198A1 MEMORY SYSTEM 审中-公开
标题翻译：记忆系统
公开(公告)号：US20120134198A1
公开(公告)日：2012-05-31
申请号：US13306175
申请日：2011-11-29
申请人： Koichiro Yamaguchi , Jin Kashiwagi
发明人： Koichiro Yamaguchi , Jin Kashiwagi
IPC分类号： G11C11/413 , G11C7/06 , G11C7/10
CPC分类号： G11C11/419 , G11C7/1006 , G11C2029/0411
摘要： A memory system includes a memory cell array including a plurality of memory cells electrically connected to pairs of bit lines once a word line is activated; latch portions connected to respective pairs of bit lines; a sense amplifier connected to the latch portions; and a control circuit configured to control the latch portions for a reading operation in order that data in all memory cells connected to the word line, once selected, come to be held in the corresponding latch portions as a group.
摘要翻译：存储器系统包括存储单元阵列，包括一旦字线被激活就电连接到位线对的多个存储器单元; 连接到相应的位线对的锁存部分; 连接到所述闩锁部分的感测放大器; 以及控制电路，被配置为控制所述锁存部分进行读取操作，以便一旦选择连接到所述字线的所有存储单元中的数据作为一组被保持在相应的锁存部分中。

5. 发明申请

US20120175726A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20120175726A1
公开(公告)日：2012-07-12
申请号：US13281705
申请日：2011-10-26
申请人： Jin Kashiwagi
发明人： Jin Kashiwagi
IPC分类号： H01L27/04
CPC分类号： H01J37/3056 , H01J2237/30466 , H01J2237/31749 , H01L21/823892 , H01L22/20 , H01L27/0207
摘要： According to one embodiment, a semiconductor device comprises a circuit portion, wells, and dummy wells. A circuit portion is formed on an upper surface of a semiconductor substrate of a first conductivity type. The wells are of a second conductivity type different from the first conductivity type. Each of wells is formed in the semiconductor substrate on an upper surface side, constitutes the circuit portion, and functions as an element. The dummy wells are of the second conductivity type. Each of the dummy wells is formed in the semiconductor substrate on the upper surface side, does not constitute the circuit portion, and does not function as an element.
摘要翻译：根据一个实施例，半导体器件包括电路部分，阱和虚拟阱。电路部分形成在第一导电类型的半导体衬底的上表面上。这些孔具有不同于第一导电类型的第二导电类型。每个阱在上表面侧的半导体衬底中形成，构成电路部分，并且用作元件。虚拟阱是第二导电类型。每个虚拟阱形成在上表面侧的半导体衬底中，不构成电路部分，并且不用作元件。

6. 发明申请

US20110176370A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20110176370A1
公开(公告)日：2011-07-21
申请号：US12885796
申请日：2010-09-20
申请人： Takatomi IZUMI , Jin Kashiwagi
发明人： Takatomi IZUMI , Jin Kashiwagi
IPC分类号： G11C16/30
CPC分类号： G11C16/08 , G11C16/30
摘要： A nonvolatile semiconductor memory comprises a memory cell array in which a plurality of memory cell transistors capable of storing data according to a threshold voltage; a row decoder having a plurality of transfer MOS transistors connected at first ends to a plurality of word lines which are respectively connected to control gate electrodes of the plurality of memory cell transistors; and a word line driver which selects supplied voltages and supplies the selected voltages to second ends of the plurality of transfer MOS transistors. The nonvolatile semiconductor memory further comprises a voltage generation circuit which supplies voltages to the word line driver; and a control circuit which controls operation of the row decoder, the word line driver and the voltage generation circuit.
摘要翻译：非易失性半导体存储器包括存储单元阵列，其中能够根据阈值电压存储数据的多个存储单元晶体管; 行解码器，其具有在第一端连接到分别连接到所述多个存储单元晶体管的控制栅电极的多个字线的多个传输MOS晶体管; 以及字线驱动器，其选择提供的电压并将所选择的电压提供给多个传输MOS晶体管的第二端。非易失性半导体存储器还包括向字线驱动器提供电压的电压产生电路; 以及控制行解码器，字线驱动器和电压产生电路的操作的控制电路。

7. 发明申请

US20070230246A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070230246A1
公开(公告)日：2007-10-04
申请号：US11690420
申请日：2007-03-23
申请人： Akira Umezawa , Jin Kashiwagi
发明人： Akira Umezawa , Jin Kashiwagi
IPC分类号： G11C16/06 , G11C11/34 , G11C29/00
CPC分类号： G11C16/26 , G11C16/04 , G11C29/021 , G11C29/028 , G11C29/24
摘要： A non-volatile semiconductor memory device comprises a redundant memory cell to store address data of a defect cell in a memory cell array. A first decoder circuit is given a first drive voltage to provide a control signal to the redundant memory cell. A dummy memory cell has a threshold voltage corresponding to the redundant memory cell. A second decoder circuit is given a second drive voltage corresponding to the first drive voltage to provide a control signal to the dummy memory cell. A comparator circuit compares data to be read out of the dummy memory cell with data actually read out of the dummy memory cell.
摘要翻译：非易失性半导体存储器件包括用于存储存储单元阵列中的缺陷单元的地址数据的冗余存储单元。第一解码器电路被给予第一驱动电压以向冗余存储器单元提供控制信号。虚拟存储单元具有对应于冗余存储单元的阈值电压。第二解码器电路被给予对应于第一驱动电压的第二驱动电压，以向虚拟存储器单元提供控制信号。比较器电路将要从虚拟存储器单元读出的数据与从虚拟存储单元实际读出的数据进行比较。

8. 发明申请

US20050012494A1 Power supply voltage lowering circuit used in semiconductor device 失效
标题翻译：电源降压电路用于半导体器件
公开(公告)号：US20050012494A1
公开(公告)日：2005-01-20
申请号：US10671339
申请日：2003-09-25
申请人： Takayuki Kawaguchi , Jin Kashiwagi
发明人： Takayuki Kawaguchi , Jin Kashiwagi
IPC分类号： G11C11/413 , G05F1/46 , G05F3/24 , H01L21/822 , H01L27/04 , G05F3/16
CPC分类号： G05F1/465
摘要： A reference voltage generating circuit generates reference voltage and outputs the thus generated reference voltage from an output terminal thereof. A voltage generating circuit lowers external power supply voltage according to the reference voltage supplied from the reference voltage generating circuit to output internal power supply voltage from an output terminal thereof. A transistor has a current path connected between a terminal to which the external power supply voltage is supplied and the output terminal of the voltage generating circuit or between the terminal to which the external power supply voltage is supplied and the output terminal of the reference voltage generating circuit and a gate supplied with constant voltage and has negative threshold voltage.
摘要翻译：参考电压产生电路产生参考电压并从其输出端输出由此产生的参考电压。电压发生电路根据从基准电压产生电路提供的参考电压降低外部电源电压，以从其输出端输出内部电源电压。晶体管具有连接在供给外部电源电压的端子与电压产生电路的输出端子之间的电流路径，或连接到供给外部电源电压的端子与产生基准电压的输出端子之间的电流通路电路和提供恒压的门，并具有负阈值电压。

9. 发明授权

US08233328B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08233328B2
公开(公告)日：2012-07-31
申请号：US12885796
申请日：2010-09-20
申请人： Takatomi Izumi , Jin Kashiwagi
发明人： Takatomi Izumi , Jin Kashiwagi
IPC分类号： G11C11/4193
CPC分类号： G11C16/08 , G11C16/30
摘要： A nonvolatile semiconductor memory comprises a memory cell array in which a plurality of memory cell transistors capable of storing data according to a threshold voltage; a row decoder having a plurality of transfer MOS transistors connected at first ends to a plurality of word lines which are respectively connected to control gate electrodes of the plurality of memory cell transistors; and a word line driver which selects supplied voltages and supplies the selected voltages to second ends of the plurality of transfer MOS transistors. The nonvolatile semiconductor memory further comprises a voltage generation circuit which supplies voltages to the word line driver; and a control circuit which controls operation of the row decoder, the word line driver and the voltage generation circuit.
摘要翻译：非易失性半导体存储器包括存储单元阵列，其中能够根据阈值电压存储数据的多个存储单元晶体管; 行解码器，其具有在第一端连接到分别连接到所述多个存储单元晶体管的控制栅电极的多个字线的多个传输MOS晶体管; 以及字线驱动器，其选择提供的电压并将所选择的电压提供给多个传输MOS晶体管的第二端。非易失性半导体存储器还包括向字线驱动器提供电压的电压产生电路; 以及控制行解码器，字线驱动器和电压产生电路的操作的控制电路。

10. 发明授权

US06927558B2 Power supply voltage lowering circuit used in semiconductor device 失效
公开(公告)号：US06927558B2
公开(公告)日：2005-08-09
申请号：US10671339
申请日：2003-09-25
申请人： Takayuki Kawaguchi , Jin Kashiwagi
发明人： Takayuki Kawaguchi , Jin Kashiwagi
IPC分类号： G11C11/413 , G05F1/46 , G05F3/24 , H01L21/822 , H01L27/04 , G05F3/16
CPC分类号： G05F1/465
摘要： A reference voltage generating circuit generates reference voltage and outputs the thus generated reference voltage from an output terminal thereof. A voltage generating circuit lowers external power supply voltage according to the reference voltage supplied from the reference voltage generating circuit to output internal power supply voltage from an output terminal thereof. A transistor has a current path connected between a terminal to which the external power supply voltage is supplied and the output terminal of the voltage generating circuit or between the terminal to which the external power supply voltage is supplied and the output terminal of the reference voltage generating circuit and a gate supplied with constant voltage and has negative threshold voltage.

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