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1. 发明授权

US06553450B1 Buffer to multiply memory interface 有权
标题翻译：缓冲区来乘以内存接口
公开(公告)号：US06553450B1
公开(公告)日：2003-04-22
申请号：US09664985
申请日：2000-09-18
申请人： Jim M. Dodd , Michael W. Williams , John B. Halbert , Randy M. Bonella , Chung Lam
发明人： Jim M. Dodd , Michael W. Williams , John B. Halbert , Randy M. Bonella , Chung Lam
IPC分类号： G06F1202
CPC分类号： G06F13/16 , Y02D10/14
摘要： Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The at least one buffer allows the memory interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the buffer. The second sub-interface is between the buffer and the memory modules. The method also includes interleaving output of the memory ranks in the memory modules, and configuring the at least one buffer to properly latch data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.
摘要翻译：公开了在芯片组和存储器数据之间提供电隔离。本公开包括在芯片组和存储器模块之间的存储器接口中提供至少一个缓冲器。每个存储器模块包括多个存储器等级。至少一个缓冲器允许将存储器接口拆分成第一和第二子接口。第一个子接口位于芯片组和缓冲区之间。第二个子接口位于缓冲区和内存模块之间。该方法还包括交织存储器模块中的存储器级别的输出，以及配置至少一个缓冲器以适当地锁存正在芯片组和存储器模块之间传输的数据。第一子接口和第二子接口彼此独立地操作，但是彼此同步。

2. 发明授权

US07249232B2 Buffering and interleaving data transfer between a chipset and memory modules 有权
标题翻译：在芯片组和存储器模块之间缓冲和交织数据传输
公开(公告)号：US07249232B2
公开(公告)日：2007-07-24
申请号：US10777921
申请日：2004-02-11
申请人： John B. Halbert , Jim M. Dodd , Chung Lam , Randy M. Bonella
发明人： John B. Halbert , Jim M. Dodd , Chung Lam , Randy M. Bonella
IPC分类号： G06F13/00 , G06F3/00 , G06F5/06
CPC分类号： G06F13/4234
摘要： Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The buffers allow the memory interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the buffers. The second sub-interface is between the buffers and the memory modules. The method also includes interleaving output of the buffers, and configuring the buffers to properly latch the data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.
摘要翻译：公开了在芯片组和存储器数据之间提供电隔离。本公开包括在芯片组和存储器模块之间的存储器接口中提供至少一个缓冲器。每个存储器模块包括多个存储器等级。这些缓冲区允许将存储器接口拆分成第一和第二子接口。第一个子接口位于芯片组和缓冲区之间。第二个子接口位于缓冲区和内存模块之间。该方法还包括交织缓冲器的输出，以及配置缓冲器以适当地锁存正在芯片组和存储器模块之间传输的数据。第一子接口和第二子接口彼此独立地操作，但是彼此同步。

3. 发明授权

US06625687B1 Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing 有权
标题翻译：存储模块采用点对点连接隔离，电压转换，数据同步和复用/解复用的结电路
公开(公告)号：US06625687B1
公开(公告)日：2003-09-23
申请号：US09665238
申请日：2000-09-18
申请人： John B. Halbert , Jim M. Dodd , Chung Lam , Randy M. Bonella
发明人： John B. Halbert , Jim M. Dodd , Chung Lam , Randy M. Bonella
IPC分类号： G06F1200
CPC分类号： G06F13/1684 , G06F13/4256 , Y02D10/14 , Y02D10/151
摘要： A plurality of memory modules interface through a daisy-chain providing a point-to-point connection for each memory module. The first and the last memory module in the daisy chain each connect to a separate memory controller port forming a ring circuit. A distinct set of signals connect the memory modules in each direction. A junction circuit in each memory module provides line isolation, a coupling to the adjoining memory modules in the daisy chain, or in the case of the first and last memory module in the daisy chain, a memory module and a memory controller, and a data synchronization circuit. Each junction circuit provides as well as voltage conversion so that the memory devices on a memory module operate at a different voltage than the memory controller, and multiplexing/de-multiplexing so that a lesser number of lines interface with each junction circuit.
摘要翻译：多个存储器模块通过菊花链接口，为每个存储器模块提供点对点连接。菊花链中的第一个和最后一个存储器模块都连接到形成环形电路的单独的存储器控制器端口。一组独特的信号在每个方向连接存储器模块。每个存储器模块中的结电路提供线路隔离，耦合到菊花链中的相邻存储器模块，或者在菊花链中的第一和最后存储器模块的情况下，存储器模块和存储器控制器以及数据同步电路每个结电路提供以及电压转换，使得存储器模块上的存储器件以与存储器控制器不同的电压工作，以及多路复用/解复用，使得较少数量的线路与每个结电路接口。

4. 发明授权

US06697888B1 Buffering and interleaving data transfer between a chipset and memory modules 有权
标题翻译：在芯片组和存储器模块之间缓冲和交织数据传输
公开(公告)号：US06697888B1
公开(公告)日：2004-02-24
申请号：US09675304
申请日：2000-09-29
申请人： John B. Halbert , Jim M. Dodd , Chung Lam , Randy M. Bonella
发明人： John B. Halbert , Jim M. Dodd , Chung Lam , Randy M. Bonella
IPC分类号： G06F300
CPC分类号： G06F13/4234
摘要： Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The buffers allow the memory interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the buffers. The second sub-interface is between the buffers and the memory modules. The method also includes interleaving output of the buffers, and configuring the buffers to properly latch the data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.
摘要翻译：公开了在芯片组和存储器数据之间提供电隔离。本公开包括在芯片组和存储器模块之间的存储器接口中提供至少一个缓冲器。每个存储器模块包括多个存储器等级。这些缓冲区允许将存储器接口拆分成第一和第二子接口。第一个子接口位于芯片组和缓冲区之间。第二个子接口位于缓冲区和内存模块之间。该方法还包括交织缓冲器的输出，以及配置缓冲器以适当地锁存正在芯片组和存储器模块之间传输的数据。第一子接口和第二子接口彼此独立地操作，但是彼此同步。

5. 发明授权

US06820163B1 Buffering data transfer between a chipset and memory modules 有权
标题翻译：缓冲芯片组和内存模块之间的数据传输
公开(公告)号：US06820163B1
公开(公告)日：2004-11-16
申请号：US09666489
申请日：2000-09-18
申请人： James A. McCall , Randy M. Bonella , John B. Halbert , Jim M. Dodd , Chung Lam
发明人： James A. McCall , Randy M. Bonella , John B. Halbert , Jim M. Dodd , Chung Lam
IPC分类号： G06F1300
CPC分类号： G11C7/1006 , G06F13/4256
摘要： Buffering data transfer between a chipset and memory modules is disclosed. The disclosure includes providing and configuring at least one buffer. The buffers are provided in an interface between a chipset and memory modules. The buffers allow the interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the at least one buffer. The second sub-interface is between the at least one buffer and the memory modules. The buffers are then configured to properly latch the data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.
摘要翻译：公开了在芯片组和存储器模块之间缓冲数据传输。本公开包括提供和配置至少一个缓冲器。缓冲器提供在芯片组和存储器模块之间的接口中。缓冲区允许将接口拆分为第一和第二子接口。第一子接口在芯片组和至少一个缓冲器之间。第二子接口位于至少一个缓冲器和存储器模块之间。然后将缓冲器配置为适当地锁存正在芯片组和存储器模块之间传输的数据。第一子接口和第二子接口彼此独立地操作，但是彼此同步。

6. 发明授权

US06317352B1 Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules 有权
标题翻译：用于在存储器控制器和存储器模块之间实现缓冲菊花链连接的装置
公开(公告)号：US06317352B1
公开(公告)日：2001-11-13
申请号：US09665196
申请日：2000-09-18
申请人： John B. Halbert , Jim M. Dodd , Chung Lam , Randy M. Bonella
发明人： John B. Halbert , Jim M. Dodd , Chung Lam , Randy M. Bonella
IPC分类号： G11C502
CPC分类号： G11C8/12 , G06F13/409 , G06F13/4256 , G11C5/02 , G11C5/14 , Y02D10/14 , Y02D10/151
摘要： A plurality of memory modules interface through a daisy-chain providing a point-to-point connection for each memory module. The first and the last memory module in the daisy chain each connect to a separate memory controller port forming a ring circuit. A distinct set of signals connect the memory modules in each direction. A junction circuit in each memory module provides line isolation, a coupling to the adjoining memory modules in the daisy chain, or in the case of the first and last memory module in the daisy chain, a memory module and a memory controller, and a data synchronization circuit. Each junction circuit provides as well as voltage conversion so that the memory devices on a memory module operate at a different voltage than the memory controller, and multiplexing/de-multiplexing so that a lesser number of lines interface with each junction circuit.
摘要翻译：多个存储器模块通过菊花链接口，为每个存储器模块提供点对点连接。菊花链中的第一个和最后一个存储器模块都连接到形成环形电路的单独的存储器控制器端口。一组独特的信号在每个方向连接存储器模块。每个存储器模块中的结电路提供线路隔离，耦合到菊花链中的相邻存储器模块，或者在菊花链中的第一和最后存储器模块的情况下，存储器模块和存储器控制器以及数据同步电路每个结电路提供以及电压转换，使得存储器模块上的存储器件以与存储器控制器不同的电压工作，以及多路复用/解复用，使得较少数量的线路与每个结电路接口。

7. 发明授权

US06400631B1 Circuit, system and method for executing a refresh in an active memory bank 有权
标题翻译：用于在活动存储体中执行刷新的电路，系统和方法
公开(公告)号：US06400631B1
公开(公告)日：2002-06-04
申请号：US09662728
申请日：2000-09-15
申请人： Michael W. Williams , Jim M. Dodd
发明人： Michael W. Williams , Jim M. Dodd
IPC分类号： G11C1304
CPC分类号： G11C11/406
摘要： A memory containing a plurality of memory banks and a plurality of sense amplifiers. Also, the memory device contains a multiplexer and logic. The logic receives a refresh request for one of the plurality of memory banks and instructs the multiplexer to select one of the plurality of sense amplifiers in response to the refresh request.
摘要翻译：一种包含多个存储体和多个读出放大器的存储器。此外，存储器件包含多路复用器和逻辑。逻辑接收对多个存储器组中的一个的刷新请求，并且指示多路复用器响应于刷新请求选择多个读出放大器之一。

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