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1. 发明申请

US20090313083A1 RENEWABLE ENERGY CALCULATOR 审中-公开
标题翻译：可再生能源计算器
公开(公告)号：US20090313083A1
公开(公告)日：2009-12-17
申请号：US12138753
申请日：2008-06-13
申请人： Jim Dillon , Ronald Blagus , Stephen Parr , Venkat Iyer , Alan Houghton
发明人： Jim Dillon , Ronald Blagus , Stephen Parr , Venkat Iyer , Alan Houghton
IPC分类号： G06Q10/00 , G06Q50/00 , G06Q40/00
CPC分类号： G06Q40/02 , G06Q10/06393 , G06Q30/02 , G06Q40/00 , Y04S10/58 , Y04S50/14
摘要： A calculator or system for evaluating renewable energies in various geospatial areas or regions and for targeting potential buyers. The calculator may have a financial model which has inputs of renewable energy data by region including respective energy outputs and monetary values. The inputs may also include financial information related to establishing renewable energies. An output from the financial model may include a scorecard of information. Also, customer information may be added to the scorecard. The scorecard may have an output that targets potential customers of renewable energies.
摘要翻译：用于评估各种地理空间地区或地区的可再生能源并针对潜在买家的计算器或系统。计算器可以具有按区域的可再生能源数据输入的财务模型，包括各自的能量输出和货币值。投入还可能包括与建立可再生能源有关的财务信息。财务模型的输出可以包括信息记分卡。此外，客户信息可以被添加到记分卡。记分卡可能具有针对可再生能源潜在客户的产出。

2. 发明授权

US08600571B2 Energy optimization system 有权
标题翻译：能源优化系统
公开(公告)号：US08600571B2
公开(公告)日：2013-12-03
申请号：US12142528
申请日：2008-06-19
申请人： Jim Dillon , Ronald Blagus , Stephen Parr , Venkat Iyer , Alan Houghton
发明人： Jim Dillon , Ronald Blagus , Stephen Parr , Venkat Iyer , Alan Houghton
IPC分类号： G05D17/00 , G06F17/00
CPC分类号： G06Q50/06 , G06Q10/04 , Y02A30/12 , Y02E40/76 , Y04S10/545 , Y04S10/60
摘要： A system for optimizing a usage of energy based on cost, carbon footprint, and/or other criteria. The usage may be optimized for the next day or more. The optimization may deal with renewable energy, grid energy and stored energy. Various inputs may be considered for optimization, which could include energy costs, weather forecasts, characteristics of renewable energy, the load and storage, and other items. The optimizer may use equipment models with numerical transfer functions to take inputs and provide optimized estimates for the next day or so of energy usage. The outputs of the models may go to an optimization algorithms module for providing an output based on the inputs. The output may provide control information for the selection and amounts of the different types of energy in a scheduled manner.
摘要翻译：基于成本，碳足迹和/或其他标准来优化能量使用的系统。可能会为第二天或更长时间优化使用。优化可能涉及可再生能源，电网能量和储能。可以考虑各种投入进行优化，其中可能包括能源成本，天气预报，可再生能源的特性，负荷和储存等。优化器可以使用具有数字传递函数的设备模型来获取输入，并为第二天的能量使用提供优化的估计。模型的输出可以转到优化算法模块，以提供基于输入的输出。输出可以按计划的方式提供用于不同类型能量的选择和量的控制信息。

3. 发明申请

US20090319090A1 ENERGY OPTIMIZATION SYSTEM 有权
标题翻译：能源优化系统
公开(公告)号：US20090319090A1
公开(公告)日：2009-12-24
申请号：US12142528
申请日：2008-06-19
申请人： Jim C. Dillon , Ronald Blagus , Stephen Parr , Venkat Iyer , Alan Houghton
发明人： Jim C. Dillon , Ronald Blagus , Stephen Parr , Venkat Iyer , Alan Houghton
IPC分类号： G06F1/26
CPC分类号： G06Q50/06 , G06Q10/04 , Y02A30/12 , Y02E40/76 , Y04S10/545 , Y04S10/60
摘要： A system for optimizing a usage of energy based on cost, carbon footprint, and/or other criteria. The usage may be optimized for the next day or more. The optimization may deal with renewable energy, grid energy and stored energy. Various inputs may be considered for optimization, which could include energy costs, weather forecasts, characteristics of renewable energy, the load and storage, and other items. The optimizer may use equipment models with numerical transfer functions to take inputs and provide optimized estimates for the next day or so of energy usage. The outputs of the models may go to an optimization algorithms module for providing an output based on the inputs. The output may provide control information for the selection and amounts of the different types of energy in a scheduled manner.
摘要翻译：基于成本，碳足迹和/或其他标准来优化能量使用的系统。可能会为第二天或更长时间优化使用。优化可能涉及可再生能源，电网能量和储能。可以考虑各种投入进行优化，其中可能包括能源成本，天气预报，可再生能源的特性，负荷和储存等。优化器可以使用具有数字传递函数的设备模型来获取输入，并为第二天的能量使用提供优化的估计。模型的输出可以转到优化算法模块，以提供基于输入的输出。输出可以按计划的方式提供用于不同类型能量的选择和量的控制信息。

4. 发明申请

US20080044946A1 SEMICONDUCTOR DIE PACKAGE USING LEADFRAME AND CLIP AND METHOD OF MANUFACTURING 失效
标题翻译：使用铅笔和夹子的半导体芯片封装及其制造方法
公开(公告)号：US20080044946A1
公开(公告)日：2008-02-21
申请号：US11856635
申请日：2007-09-17
申请人： Erwin Victor Cruz , Elsie Cabahug , Ti Ching Shian , Venkat Iyer
发明人： Erwin Victor Cruz , Elsie Cabahug , Ti Ching Shian , Venkat Iyer
IPC分类号： H01L21/60
CPC分类号： H01L21/6835 , H01L21/561 , H01L21/568 , H01L23/49548 , H01L23/49551 , H01L23/49562 , H01L24/33 , H01L24/37 , H01L24/39 , H01L24/83 , H01L24/97 , H01L2224/16245 , H01L2224/29109 , H01L2224/29111 , H01L2224/29116 , H01L2224/2919 , H01L2224/32057 , H01L2224/32245 , H01L2224/37147 , H01L2224/73253 , H01L2224/83385 , H01L2224/83801 , H01L2224/8485 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01057 , H01L2924/01078 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/12032 , H01L2924/12041 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2924/19043 , H01L2924/3651 , H01L2224/83 , H01L2924/00 , H01L2924/00014 , H01L2924/00012
摘要： A clip structure for a semiconductor package is disclosed. The clip structure includes a major portion, at least one pedestal extending from the major portion, a downset portion, and a lead portion. The downset portion is between the lead portion and the major portion. The clip structure can be used in a MLP (micro-leadframe package).
摘要翻译：公开了一种用于半导体封装的夹子结构。夹子结构包括主要部分，从主要部分延伸的至少一个基座，下降部分和引导部分。凹陷部分在引导部分和主要部分之间。夹子结构可用于MLP（微引线框封装）。

5. 发明申请

US20070249092A1 Semiconductor die package including multiple dies and a common node structure 有权
标题翻译：半导体管芯封装包括多个管芯和一个共同的节点结构
公开(公告)号：US20070249092A1
公开(公告)日：2007-10-25
申请号：US11410504
申请日：2006-04-24
申请人： Rajeev Joshi , Venkat Iyer , Jonathan Klein
发明人： Rajeev Joshi , Venkat Iyer , Jonathan Klein
IPC分类号： H01L21/00
CPC分类号： H01L23/49575 , H01L23/492 , H01L23/49524 , H01L23/49562 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L2224/37147 , H01L2224/40245 , H01L2224/48137 , H01L2224/48247 , H01L2224/49171 , H01L2224/73253 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die. The semiconductor die package includes a second semiconductor die mounted on the substrate, where second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die. A substantially planar conductive node clip electrically communicates the first output region in the first semiconductor die and the second input region in the second semiconductor die. The first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.
摘要翻译：公开了一种能够安装在母板上的半导体管芯封装。半导体管芯封装包括衬底和安装在衬底上的第一半导体管芯，其中第一半导体管芯包括第一垂直器件，第一垂直器件包括第一半导体管芯的相对表面处的第一输入区域和第一输出区域。半导体管芯封装包括安装在基板上的第二半导体管芯，其中第二半导体管芯包括第二垂直器件，该第二垂直器件包括在第二半导体管芯的相对表面处的第二输入区域和第二输出区域。基本上平面的导电节点夹将第一半导体管芯中的第一输出区域和第二半导体管芯中的第二输入区域电连通。第一半导体管芯和第二半导体管芯位于衬底和导电节点夹之间。

6. 发明授权

US06724848B1 Sync regeneration in a universal serial bus 有权
标题翻译：通用串行总线同步再生
公开(公告)号：US06724848B1
公开(公告)日：2004-04-20
申请号：US09519511
申请日：2000-03-06
申请人： Venkat Iyer
发明人： Venkat Iyer
IPC分类号： H04L700
CPC分类号： H04L7/046 , H04L7/005
摘要： A Universal Serial Bus repeater is provided, comprising a method and apparatus for detecting a specified data pattern and regenerating or retransmitting the recognized data pattern. In some embodiments, the invention recognizes an end of sync signal, and is operable to retransmit the end of sync signal and the following data that is presumed to be valid as a result of sync recognition. In other embodiments, the invention recognizes and retransmits a properly aligned end of packet signal, the size of which is dependent on detection of whether the end of packet signal is a part of a start of frame packet.
摘要翻译：提供了一种通用串行总线中继器，包括用于检测指定数据模式并重新生成或重新发送所识别的数据模式的方法和装置。在一些实施例中，本发明识别同步信号的结束，并且可操作用于重传同步信号的结束以及作为同步识别的结果被认为是有效的后续数据。在其他实施例中，本发明识别和重新发送分组信号的正确对齐端，其大小取决于分组信号的结束是否是帧分组开始的一部分。

7. 发明授权

US06629186B1 Bus controller and associated device drivers for use to control a peripheral bus having at least one store-and-forward segment 失效
标题翻译：总线控制器和相关设备驱动器，用于控制具有至少一个存储转发段的外围总线
公开(公告)号：US06629186B1
公开(公告)日：2003-09-30
申请号：US09309088
申请日：1999-05-10
申请人： John I. Garney , John S. Howard , Venkat Iyer
发明人： John I. Garney , John S. Howard , Venkat Iyer
IPC分类号： G06F1312
CPC分类号： G06F13/102
摘要： A bus controller and its associated device drivers are provided to a digital system to operate and control a peripheral bus, including the selective operation of at least a first portion of the peripheral bus in a store-and-forward manner. The device drivers include a number of programming instructions. Upon programmed with the programming instructions, a digital system is enabled to operate the bus controller to facilitate communication with a first bus agent in this first portion. The programming instructions package a number of request packets destined for the first bus agent into a multi-packet package, schedule the multi-packet package to be transmitted in bulk, at a first communication speed, to a first hub in the first portion, for the first hub to buffer the request packets, and then forward the request packets to the first bus agent, on a packet-by-packet basis and at a second communication speed. In one embodiment, the second communication speed is slower than the first communication speed. In one embodiment, the programming instructions further schedule communications destined for a second bus agent of this first portion, for transmission to the first hub, at the first communication speed, for the first hub to repeat the communications for the second bus agent without buffering, at also the first communication speed.
摘要翻译：将总线控制器及其相关的设备驱动器提供给数字系统以操作和控制外围总线，包括以存储和转发的方式选择性地操作外围总线的至少第一部分。设备驱动程序包括一些编程指令。在使用编程指令编程时，数字系统能够操作总线控制器以便于在该第一部分中与第一总线代理的通信。编程指令将目的地为第一总线代理的多个请求分组封装成多分组包，将以多个第一通信速度批量发送的多分组分组调度到第一部分中的第一集线器，以便第一集线器缓冲请求分组，然后逐个分组地以第二通信速度将请求分组转发到第一总线代理。在一个实施例中，第二通信速度比第一通信速度慢。在一个实施例中，编程指令进一步调度目的地为该第一部分的第二总线代理的通信，用于以第一通信速度传输到第一集线器，以使第一集线器重复第二总线代理的通信而不进行缓冲，也是第一个通信速度。

8. 发明授权

US08664752B2 Semiconductor die package and method for making the same 有权
标题翻译：半导体管芯封装及其制造方法
公开(公告)号：US08664752B2
公开(公告)日：2014-03-04
申请号：US13430347
申请日：2012-03-26
申请人： Oseob Jeon , Yoonhwa Choi , Boon Huan Gooi , Maria Cristina B. Estacio , David Chong , Tan Teik Keng , Shibaek Nam , Rajeev Joshi , Chung-Lin Wu , Venkat Iyer , Lay Yeap Lim , Byoung-Ok Lee
发明人： Oseob Jeon , Yoonhwa Choi , Boon Huan Gooi , Maria Cristina B. Estacio , David Chong , Tan Teik Keng , Shibaek Nam , Rajeev Joshi , Chung-Lin Wu , Venkat Iyer , Lay Yeap Lim , Byoung-Ok Lee
IPC分类号： H01L23/495
CPC分类号： H01L24/29 , H01L21/561 , H01L23/3121 , H01L23/4951 , H01L23/49558 , H01L23/49562 , H01L23/49575 , H01L23/49861 , H01L24/32 , H01L24/36 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/97 , H01L25/0655 , H01L2223/54406 , H01L2223/54486 , H01L2224/16 , H01L2224/291 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29299 , H01L2224/293 , H01L2224/32057 , H01L2224/32225 , H01L2224/40245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45169 , H01L2224/45565 , H01L2224/456 , H01L2224/45644 , H01L2224/45669 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/48237 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/49113 , H01L2224/4943 , H01L2224/73204 , H01L2224/73265 , H01L2224/83192 , H01L2224/83385 , H01L2224/83801 , H01L2224/8385 , H01L2224/85013 , H01L2224/97 , H01L2924/00013 , H01L2924/00014 , H01L2924/0132 , H01L2924/014 , H01L2924/07802 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2924/1815 , H01L2924/19043 , H01L2924/30107 , H01L2224/85 , H01L2924/00 , H01L2924/0105 , H01L2924/01082 , H01L2924/00012 , H01L2224/13111 , H01L2924/0665 , H01L2224/29099 , H01L2224/29199 , H01L2224/37099
摘要： Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.
摘要翻译：公开了半导体管芯封装。示例性半导体管芯封装包括预成型衬底。预成型基板可以具有附接到其上的半导体管芯，并且封装材料可以设置在半导体管芯上方。

9. 发明授权

US08212361B2 Semiconductor die package including multiple dies and a common node structure 有权
标题翻译：半导体管芯封装包括多个管芯和一个共同的节点结构
公开(公告)号：US08212361B2
公开(公告)日：2012-07-03
申请号：US12575641
申请日：2009-10-08
申请人： Rajeev Joshi , Venkat Iyer , Jonathan Klein
发明人： Rajeev Joshi , Venkat Iyer , Jonathan Klein
IPC分类号： H01L23/48
CPC分类号： H01L23/49575 , H01L23/492 , H01L23/49524 , H01L23/49562 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L2224/37147 , H01L2224/40245 , H01L2224/48137 , H01L2224/48247 , H01L2224/49171 , H01L2224/73253 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die. The semiconductor die package includes a second semiconductor die mounted on the substrate, where second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die. A substantially planar conductive node clip electrically communicates the first output region in the first semiconductor die and the second input region in the second semiconductor die. The first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.
摘要翻译：公开了一种能够安装在母板上的半导体管芯封装。半导体管芯封装包括衬底和安装在衬底上的第一半导体管芯，其中第一半导体管芯包括第一垂直器件，第一垂直器件包括第一半导体管芯的相对表面处的第一输入区域和第一输出区域。半导体管芯封装包括安装在基板上的第二半导体管芯，其中第二半导体管芯包括第二垂直器件，该第二垂直器件包括在第二半导体管芯的相对表面处的第二输入区域和第二输出区域。基本上平面的导电节点夹将第一半导体管芯中的第一输出区域和第二半导体管芯中的第二输入区域电连通。第一半导体管芯和第二半导体管芯位于衬底和导电节点夹之间。

10. 发明授权

US08058107B2 Semiconductor die package using leadframe and clip and method of manufacturing 失效
标题翻译：使用引线框和夹子的半导体管芯封装及其制造方法
公开(公告)号：US08058107B2
公开(公告)日：2011-11-15
申请号：US11856635
申请日：2007-09-17
申请人： Erwin Victor R. Cruz , Elsie Cabahug , Ti Ching Shian , Venkat Iyer
发明人： Erwin Victor R. Cruz , Elsie Cabahug , Ti Ching Shian , Venkat Iyer
IPC分类号： H01L21/00 , H01L23/495
CPC分类号： H01L21/6835 , H01L21/561 , H01L21/568 , H01L23/49548 , H01L23/49551 , H01L23/49562 , H01L24/33 , H01L24/37 , H01L24/39 , H01L24/83 , H01L24/97 , H01L2224/16245 , H01L2224/29109 , H01L2224/29111 , H01L2224/29116 , H01L2224/2919 , H01L2224/32057 , H01L2224/32245 , H01L2224/37147 , H01L2224/73253 , H01L2224/83385 , H01L2224/83801 , H01L2224/8485 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01057 , H01L2924/01078 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/12032 , H01L2924/12041 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2924/19043 , H01L2924/3651 , H01L2224/83 , H01L2924/00 , H01L2924/00014 , H01L2924/00012
摘要： A clip structure for a semiconductor package is disclosed. The clip structure includes a major portion, at least one pedestal extending from the major portion, a downset portion, and a lead portion. The downset portion is between the lead portion and the major portion. The clip structure can be used in a MLP (micro-leadframe package).
摘要翻译：公开了一种用于半导体封装的夹子结构。夹子结构包括主要部分，从主要部分延伸的至少一个基座，下降部分和引导部分。凹陷部分在引导部分和主要部分之间。夹子结构可用于MLP（微引线框封装）。

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