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1. 发明申请

US20100148758A1 SYSTEMS AND METHODS FOR ON-CHIP POWER MANAGEMENT 有权
标题翻译：片上电源管理系统与方法
公开(公告)号：US20100148758A1
公开(公告)日：2010-06-17
申请号：US12691345
申请日：2010-01-21
申请人： Jien-Chung Lo , Chuen-Song Chen
发明人： Jien-Chung Lo , Chuen-Song Chen
IPC分类号： G01R11/00
CPC分类号： G01R21/00
摘要： A power measurement system is disclosed for use on an integrated circuit for measuring the power used by the integrated circuit. The power measurement system includes a low-dropout voltage regulator and a signal input unit. The low-dropout voltage regulator includes a power transistor that couples a supply voltage to a circuit to be powered by the supply voltage, and the low-dropout voltage regulator provides an internal adjustment signal (Vsen) for adjusting the internal resistance of the power transistor. The signal input unit receives the internal adjustment signal (Vsen) and provides a power measurement signal responsive to the internal adjustment signal (Vsen).
摘要翻译：公开了用于测量集成电路使用的功率的集成电路的功率测量系统。功率测量系统包括一个低压差稳压器和一个信号输入单元。低压差稳压器包括将电源电压耦合到由电源电压供电的电路的功率晶体管，并且低压差稳压器提供用于调节功率晶体管的内部电阻的内部调整信号（Vsen）。信号输入单元接收内部调整信号（Vsen），并根据内部调整信号（Vsen）提供功率测量信号。

2. 发明申请

US20090039848A1 SYSTEMS AND METHODS FOR ON-CHIP POWER MANAGEMENT 审中-公开
标题翻译：片上电源管理系统与方法
公开(公告)号：US20090039848A1
公开(公告)日：2009-02-12
申请号：US12203529
申请日：2008-09-03
申请人： Jien-Chung Lo , Chuen-Song Chen
发明人： Jien-Chung Lo , Chuen-Song Chen
IPC分类号： G05F1/10
CPC分类号： G01R21/00
摘要： A power measurement system is disclosed for use on an integrated circuit for measuring the power used by the integrated circuit. The power measurement system includes a low-dropout voltage regulator and a signal input unit. The low-dropout voltage regulator includes a power transistor that couples a supply voltage to a circuit to be powered by the supply voltage, and the low-dropout voltage regulator provides an internal adjustment signal (Vsen) for adjusting the internal resistance of the power transistor. The signal input unit receives the internal adjustment signal (Vsen) and provides a power measurement signal responsive to the internal adjustment signal (Vsen).
摘要翻译：公开了用于测量集成电路使用的功率的集成电路的功率测量系统。功率测量系统包括一个低压差稳压器和一个信号输入单元。低压差稳压器包括将电源电压耦合到由电源电压供电的电路的功率晶体管，并且低压差稳压器提供用于调节功率晶体管的内部电阻的内部调整信号（Vsen）。信号输入单元接收内部调整信号（Vsen），并根据内部调整信号（Vsen）提供功率测量信号。

3. 发明授权

US07902802B2 Systems and methods for on-chip power management 有权
标题翻译：用于片上电源管理的系统和方法
公开(公告)号：US07902802B2
公开(公告)日：2011-03-08
申请号：US12691345
申请日：2010-01-21
申请人： Jien-Chung Lo , Chuen-Song Chen
发明人： Jien-Chung Lo , Chuen-Song Chen
IPC分类号： G05F1/40
CPC分类号： G01R21/00
摘要： A power measurement system is disclosed for use on an integrated circuit for measuring the power used by the integrated circuit. The power measurement system includes a low-dropout voltage regulator and a signal input unit. The low-dropout voltage regulator includes a power transistor that couples a supply voltage to a circuit to be powered by the supply voltage, and the low-dropout voltage regulator provides an internal adjustment signal (Vsen) for adjusting the internal resistance of the power transistor. The signal input unit receives the internal adjustment signal (Vsen) and provides a power measurement signal responsive to the internal adjustment signal (Vsen).
摘要翻译：公开了用于测量集成电路使用的功率的集成电路的功率测量系统。功率测量系统包括一个低压差稳压器和一个信号输入单元。低压差稳压器包括将电源电压耦合到由电源电压供电的电路的功率晶体管，并且低压差稳压器提供用于调节功率晶体管的内部电阻的内部调整信号（Vsen）。信号输入单元接收内部调整信号（Vsen），并根据内部调整信号（Vsen）提供功率测量信号。

4. 发明申请

US20050116759A1 Programmable jitter signal generator 有权
标题翻译：可编程抖动信号发生器
公开(公告)号：US20050116759A1
公开(公告)日：2005-06-02
申请号：US10725847
申请日：2003-12-02
申请人： Keith Jenkins , Jien-Chung Lo , Peilin Song , Tian Xia
发明人： Keith Jenkins , Jien-Chung Lo , Peilin Song , Tian Xia
IPC分类号： G01R31/317 , G06F1/03 , G06F1/04 , H03K5/00 , H03K5/13 , H03K5/15
CPC分类号： G01R31/31709 , G01R31/31727 , G06F1/03 , H03K5/133 , H03K5/1506 , H03K2005/00058
摘要： A programmable jitter signal generator is provided that includes a jitter distribution control unit, a selection unit in signal communication with the jitter distribution control unit, and a delay unit in signal communication with the selection unit; and a corresponding method of generating a programmable jitter signal includes programming a control unit, receiving a reference signal, delaying the received reference signal by a multiple of a base time increment, and selecting a delayed reference signal delayed by a desired multiple of the base time increment in accordance with the programmed control unit.
摘要翻译：提供了一种可编程抖动信号发生器，其包括抖动分布控制单元，与抖动分布控制单元进行信号通信的选择单元，以及与选择单元进行信号通信的延迟单元; 并且产生可编程抖动信号的相应方法包括编程控制单元，接收参考信号，将接收到的参考信号延迟基准时间增量的倍数，以及选择延迟基准时间的期望倍数的延迟参考信号根据编程的控制单元增量。

5. 发明授权

US07095264B2 Programmable jitter signal generator 有权
标题翻译：可编程抖动信号发生器
公开(公告)号：US07095264B2
公开(公告)日：2006-08-22
申请号：US10725847
申请日：2003-12-02
申请人： Keith A. Jenkins , Jien-Chung Lo , Peilin Song , Tian Xia
发明人： Keith A. Jenkins , Jien-Chung Lo , Peilin Song , Tian Xia
IPC分类号： H03H11/26
CPC分类号： G01R31/31709 , G01R31/31727 , G06F1/03 , H03K5/133 , H03K5/1506 , H03K2005/00058
摘要： A programmable jitter signal generator is provided that includes a jitter distribution control unit, a selection unit in signal communication with the jitter distribution control unit, and a delay unit in signal communication with the selection unit; and a corresponding method of generating a programmable jitter signal includes programming a control unit, receiving a reference signal, delaying the received reference signal by a multiple of a base time increment, and selecting a delayed reference signal delayed by a desired multiple of the base time increment in accordance with the programmed control unit.
摘要翻译：提供了一种可编程抖动信号发生器，其包括抖动分布控制单元，与抖动分布控制单元进行信号通信的选择单元，以及与选择单元进行信号通信的延迟单元; 并且产生可编程抖动信号的相应方法包括编程控制单元，接收参考信号，将接收到的参考信号延迟基准时间增量的倍数，以及选择延迟基准时间的期望倍数的延迟参考信号根据编程的控制单元增量。

6. 发明授权

US5457702A Check bit code circuit for simultaneous single bit error correction and burst error detection 失效
标题翻译：检查同步单比特纠错和突发错误检测的位代码电路
公开(公告)号：US5457702A
公开(公告)日：1995-10-10
申请号：US153453
申请日：1993-11-05
申请人： Everett L. Williams, III , Harold L. Martin , Jien-Chung Lo
发明人： Everett L. Williams, III , Harold L. Martin , Jien-Chung Lo
IPC分类号： G06F11/10 , H03M13/09 , H03M13/19 , H03M13/43 , H03M13/00
CPC分类号： H03M13/43 , G06F11/1028 , H03M13/19 , H03M13/17
摘要： A system for correcting a single bit error and detecting burst errors is provided. A check bit generator generates partition check bits and burst check bits based on a H-parity matrix data regeneration scheme which provides an a single error correction and multiple bit error detection code which is linear and has the property of self orthogonality within a subclass of self orthogonal codes exclusive of Latin square codes. These check bits provide two independent sources for ascertaining the correct value for any given data bit. An error corrector and detector takes as input the data bits and check bits and provides a corrected data bit output as well as a set of error status lines. The error corrector and detector consists of Error Corrector, error corrector/detector and Error Status modules. The Error Corrector and error corrector/detector modules run in parallel providing a high speed Error Correction and Detection implementation, and providing a simplicity of logic structure compatible with application specific integrated circuit (ASIC) design and production processes.
摘要翻译：提供了用于校正单个位错误并检测突发错误的系统。校验位生成器基于H奇偶校验矩阵数据再生方案产生分区校验位和突发校验位，该方案提供单个纠错和多位错误检测码，其是线性的并且具有自身子类内的自正性不包括拉丁方码的正交码。这些检查位提供两个独立的源，用于确定任何给定数据位的正确值。误差校正器和检测器将数据位和校验位作为输入，并提供校正的数据位输出以及一组错误状态行。误差校正器和检测器由误差校正器，误差校正器/检测器和误差状态模块组成。误差校正器和误差校正器/检测器模块并行运行，提供高速误差校正和检测实现，并提供与专用集成电路（ASIC）设计和生产过程兼容的逻辑结构的简单性。

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