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1. 发明申请

US20120072880A1 Sensitivity-based complex statistical modeling for random on-chip variation 有权
标题翻译：基于敏感度的随机片上变化的复杂统计建模
公开(公告)号：US20120072880A1
公开(公告)日：2012-03-22
申请号：US13199222
申请日：2011-08-23
申请人： Jiayong Le , Mustafa Celik , Guy Maor , Ayhan Mutlu
发明人： Jiayong Le , Mustafa Celik , Guy Maor , Ayhan Mutlu
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F17/5068 , G06F2217/84
摘要： The invention provides a method for performing statistical static timing analysis using a novel on-chip variation model, referred to as Sensitivity-based Complex Statistical On-Chip Variation (SCS-OCV).SCS-OCV introduces complex variation concept to resolve the blocking technical issue of combining local random variations, enabling accurate calculation of statistical variations with correlations, such as common-path pessimism removal (CPPR).SCS-OCV proposes practical statistical min/max operations for random variations that can guarantee pessimism at nominal and targeted N-sigma corner, and extends the method to handle complex variations, enabling graph-based full arrival/required time propagation under variable compaction.SCS-OCV provides a statistical corner evaluation method for complex random variables that can transform vector-based parametric timing information to the single-value corner-based timing report, and based on the method derives equations to bridge POCV/SSTA with LOCV. This significantly reduces the learning curve and increases the usage of the technology, being more easily adopted by the industry.
摘要翻译：本发明提供一种用于使用称为基于灵敏度的复杂统计片上变化（SCS-OCV）的新颖的片上变化模型来执行统计静态时序分析的方法。 SCS-OCV引入了复杂的变异概念，以解决组合局部随机变量的阻塞技术问题，从而能够准确计算统计变异与相关性，如共路径悲观消除（CPPR）。 SCS-OCV为随机变化提供了实用的统计最小/最大运算，可以保证名义和目标N-Σ角的悲观，并扩展了处理复杂变化的方法，从而在可变压缩下实现了基于图形的完全到达/所需时间传播。 SCS-OCV为复杂的随机变量提供了统计角点评估方法，可以将基于矢量的参数定时信息转换为基于单值角的定时报告，并且基于该方法得出方程来将POCV / SSTA与LOCV桥接。这显着降低了学习曲线，增加了该技术的使用，更容易被行业所采纳。

2. 发明授权

US08407640B2 Sensitivity-based complex statistical modeling for random on-chip variation 有权
标题翻译：基于敏感度的随机片上变化的复杂统计建模
公开(公告)号：US08407640B2
公开(公告)日：2013-03-26
申请号：US13199222
申请日：2011-08-23
申请人： Jiayong Le , Mustafa Celik , Guy Maor , Ayhan Mutlu
发明人： Jiayong Le , Mustafa Celik , Guy Maor , Ayhan Mutlu
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F17/5068 , G06F2217/84
摘要： The invention provides a method for performing statistical static timing analysis using a novel on-chip variation model, referred to as Sensitivity-based Complex Statistical On-Chip Variation (SCS-OCV). SCS-OCV introduces complex variation concept to resolve the blocking technical issue of combining local random variations, enabling accurate calculation of statistical variations with correlations, such as common-path pessimism removal (CPPR). SCS-OCV proposes practical statistical min/max operations for random variations that can guarantee pessimism at nominal and targeted N-sigma corner, and extends the method to handle complex variations, enabling graph-based full arrival/required time propagation under variable compaction. SCS-OCV provides a statistical corner evaluation method for complex random variables that can transform vector-based parametric timing information to the single-value corner-based timing report, and based on the method derives equations to bridge POCV/SSTA with LOCV. This significantly reduces the learning curve and increases the usage of the technology, being more easily adopted by the industry.
摘要翻译：本发明提供一种用于使用称为基于灵敏度的复杂统计片上变化（SCS-OCV）的新颖的片上变化模型来执行统计静态时序分析的方法。 SCS-OCV引入了复杂的变异概念，以解决组合局部随机变量的阻塞技术问题，从而能够准确计算统计变异与相关性，如共路径悲观消除（CPPR）。 SCS-OCV为随机变量提供了实用的统计最小/最大运算，可以保证名义和目标N-σ角的悲观，并扩展了处理复杂变化的方法，从而在可变压缩下实现了基于图形的全到达/所需时间传播。 SCS-OCV为复杂的随机变量提供了统计角点评估方法，可以将基于矢量的参数定时信息转换为基于单值角的定时报告，并且基于该方法得出方程来将POCV / SSTA与LOCV桥接。这显着降低了学习曲线，增加了该技术的使用，更容易被行业所采纳。

3. 发明申请

US20130179851A1 STATISTICAL CORNER EVALUATION FOR COMPLEX ON CHIP VARIATION MODEL 有权
标题翻译：统计角度对芯片变化模型的复杂度评估
公开(公告)号：US20130179851A1
公开(公告)日：2013-07-11
申请号：US13784701
申请日：2013-03-04
申请人： Jiayong Le , Mustafa Celik , Guy Maor , Ayhan Mutlu
发明人： Jiayong Le , Mustafa Celik , Guy Maor , Ayhan Mutlu
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F17/5068 , G06F2217/84
摘要： The invention provides a method for performing statistical static timing analysis using a novel on-chip variation model, referred to as Sensitivity-based Complex Statistical On-Chip Variation (SCS-OCV).SCS-OCV introduces complex variation concept to resolve the blocking technical issue of combining local random variations, enabling accurate calculation of statistical variations with correlations, such as common-path pessimism removal (CPPR).SCS-OCV proposes practical statistical min/max operations for random variations that can guarantee pessimism at nominal and targeted N-sigma corner, and extends the method to handle complex variations, enabling graph-based full arrival/required time propagation under variable compaction.SCS-OCV provides a statistical corner evaluation method for complex random variables that can transform vector-based parametric timing information to the single-value corner-based timing report, and based on the method derives equations to bridge POCV/SSTA with LOCV. This significantly reduces the learning curve and increases the usage of the technology, being more easily adopted by the industry.
摘要翻译：本发明提供一种用于使用称为基于灵敏度的复杂统计片上变化（SCS-OCV）的新颖的片上变化模型来执行统计静态时序分析的方法。 SCS-OCV引入了复杂的变异概念，以解决组合局部随机变量的阻塞技术问题，从而能够准确计算统计变异与相关性，如共路径悲观消除（CPPR）。 SCS-OCV为随机变量提供了实用的统计最小/最大运算，可以保证名义和目标N-σ角的悲观，并扩展了处理复杂变化的方法，从而在可变压缩下实现了基于图形的全到达/所需时间传播。 SCS-OCV为复杂的随机变量提供了统计角点评估方法，可以将基于矢量的参数定时信息转换为基于单值角的定时报告，并且基于该方法得出方程来将POCV / SSTA与LOCV桥接。这显着降低了学习曲线，增加了该技术的使用，更容易被行业所采纳。

4. 发明授权

US08555222B2 Statistical corner evaluation for complex on chip variation model 有权
标题翻译：复杂的片上变异模型的统计角度评估
公开(公告)号：US08555222B2
公开(公告)日：2013-10-08
申请号：US13784701
申请日：2013-03-04
申请人： Jiayong Le , Mustafa Celik , Guy Maor , Ayhan Mutlu
发明人： Jiayong Le , Mustafa Celik , Guy Maor , Ayhan Mutlu
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F17/5068 , G06F2217/84
摘要： The invention provides a method for performing statistical static timing analysis using a novel on-chip variation model, referred to as Sensitivity-based Complex Statistical On-Chip Variation (SCS-OCV). SCS-OCV introduces complex variation concept to resolve the blocking technical issue of combining local random variations, enabling accurate calculation of statistical variations with correlations, such as common-path pessimism removal (CPPR). SCS-OCV proposes practical statistical min/max operations for random variations that can guarantee pessimism at nominal and targeted N-sigma corner, and extends the method to handle complex variations, enabling graph-based full arrival/required time propagation under variable compaction. SCS-OCV provides a statistical corner evaluation method for complex random variables that can transform vector-based parametric timing information to the single-value corner-based timing report, and based on the method derives equations to bridge POCV/SSTA with LOCV. This significantly reduces the learning curve and increases the usage of the technology, being more easily adopted by the industry.
摘要翻译：本发明提供一种用于使用称为基于灵敏度的复杂统计片上变化（SCS-OCV）的新颖的片上变化模型来执行统计静态时序分析的方法。 SCS-OCV引入了复杂的变异概念，以解决组合局部随机变量的阻塞技术问题，从而能够准确计算统计变异与相关性，如共路径悲观消除（CPPR）。 SCS-OCV为随机变量提供了实用的统计最小/最大运算，可以保证名义和目标N-σ角的悲观，并扩展了处理复杂变化的方法，从而在可变压缩下实现了基于图形的全到达/所需时间传播。 SCS-OCV为复杂的随机变量提供了统计角点评估方法，可以将基于矢量的参数定时信息转换为基于单值角的定时报告，并且基于该方法得出方程来将POCV / SSTA与LOCV桥接。这显着降低了学习曲线，增加了该技术的使用，更容易被行业所采纳。

5. 发明申请

US20100131911A1 Method and system for High Speed and Low Memory Footprint Static Timing Analysis 有权
标题翻译：高速和低内存占位静态时序分析方法与系统
公开(公告)号：US20100131911A1
公开(公告)日：2010-05-27
申请号：US12451308
申请日：2008-05-16
申请人： Guy Maor , Chih-Wei Jim Chang , Yuji Kukimoto , Haobin Li
发明人： Guy Maor , Chih-Wei Jim Chang , Yuji Kukimoto , Haobin Li
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5031
摘要： The invention provides a method and system for performing Static Timing Analysis on SoC (System on a Chip) designs. The invention solves a longstanding problem with timing analysis of designs, namely, the ability to multi-thread the design under analysis. The invention provides for slicing a design into levels, further decomposing each level into gates, and the multi-threaded processing of gates so that the solution of large design analysis is generated significantly faster than current approaches. Further, the invention provides that only one level exists in the RAM at any time. Once the arrival time on the level is computed, the data is saved to disk immediately. Because the memory footprint is sub-linear to the size of the design, entire system-on-a chip designs may be nm on inexpensive, off-the-shelf hardware.
摘要翻译：本发明提供了一种用于在SoC（片上系统）设计上进行静态时序分析的方法和系统。本发明解决了设计时序分析的长期问题，即分析设计多线程的能力。本发明提供了将设计切片成级别，将每个级别进一步分解成门，以及门的多线程处理，使得大规模设计分析的解决方案比当前方法快得多。此外，本发明提供了在RAM中只有一个级别。一旦计算了该级别的到达时间，数据将立即保存到磁盘。由于内存占用空间与设计的尺寸是亚线性的，因此整个系统级芯片设计可以在廉价的现成硬件上运行。

6. 发明授权

US08504960B2 Method and system for high speed and low memory footprint static timing analysis 有权
标题翻译：高速和低内存占用静态时序分析方法和系统
公开(公告)号：US08504960B2
公开(公告)日：2013-08-06
申请号：US12451308
申请日：2008-05-16
申请人： Guy Maor , Chih-Wei Jim Chang , Yuji Kukimoto , Haobin Li
发明人： Guy Maor , Chih-Wei Jim Chang , Yuji Kukimoto , Haobin Li
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5068 , G06F17/5031
摘要： The invention provides a method and system for performing Static Timing Analysis on SoC (System on a Chip) designs. The invention solves a longstanding problem with timing analysis of designs, namely, the ability to multi-thread the design under analysis. The invention provides for slicing a design into levels, further decomposing each level into gates, and the multi-threaded processing of gates so that the solution of large design analysis is generated significantly faster than current approaches. Further, the invention provides that only one level exists in the RAM at any time. Once the arrival time on the level is computed, the data is saved to disk immediately. Because the memory footprint is sub-linear to the size of the design, entire system-on-a chip designs may be nm on inexpensive, off-the-shelf hardware.
摘要翻译：本发明提供了一种用于在SoC（片上系统）设计上进行静态时序分析的方法和系统。本发明解决了设计时序分析的长期问题，即分析设计多线程的能力。本发明提供了将设计切片成级别，将每个级别进一步分解成门，以及门的多线程处理，使得大规模设计分析的解决方案比当前方法快得多。此外，本发明提供了在RAM中只有一个级别。一旦计算了该级别的到达时间，数据将立即保存到磁盘。由于内存占用空间与设计的尺寸是亚线性的，因此整个系统级芯片设计可以在廉价的现成硬件上运行。

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