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1. 发明申请

US20080308879A1 MOS STRUCTURES WITH CONTACT PROJECTIONS FOR LOWER CONTACT RESISTANCE AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：具有接触电极的接触电极的MOS结构及其制造方法
公开(公告)号：US20080308879A1
公开(公告)日：2008-12-18
申请号：US11762133
申请日：2007-06-13
申请人： Jianhong ZHU , Fred HAUSE , David WU
发明人： Jianhong ZHU , Fred HAUSE , David WU
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28518 , H01L21/28247 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/7833
摘要： MOS structures with contact projections for lower contact resistance and methods for fabricating such MOS structures have been provided. In an embodiment, a method comprises providing a semiconductor substrate, fabricating a gate stack on the substrate, and forming a contact projection on the substrate. Ions of a conductivity-determining type are implanted within the substrate using the gate stack as an ion implantation mask to form impurity-doped regions within the substrate. A metal silicide layer is formed on the contact projection and a contact is formed to the metal silicide layer. The contact is in electrical communication with the impurity-doped regions via the contact projection.
摘要翻译：已经提供了具有用于较低接触电阻的接触突起的MOS结构以及用于制造这种MOS结构的方法。在一个实施例中，一种方法包括提供半导体衬底，在衬底上制造栅极堆叠，以及在衬底上形成接触突起。使用栅极堆叠作为离子注入掩模将电导率确定类型的离子注入到衬底内，以在衬底内形成杂质掺杂区域。在接触突起上形成金属硅化物层，并且与金属硅化物层形成接触。触点通过接触突起与杂质掺杂区电连通。

2. 发明申请

US20080296682A1 MOS STRUCTURES WITH REMOTE CONTACTS AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：具有远程联系的MOS结构及其制造方法
公开(公告)号：US20080296682A1
公开(公告)日：2008-12-04
申请号：US11755930
申请日：2007-05-31
申请人： Jianhong ZHU , Jinrong ZHOU , David WU , James F. BULLER
发明人： Jianhong ZHU , Jinrong ZHOU , David WU , James F. BULLER
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L21/84 , H01L21/76895 , H01L21/823412 , H01L21/823425 , H01L21/823475 , H01L27/1203 , H01L29/7843
摘要： MOS structures with remote contacts and methods for fabricating such MOS structures are provided. In one embodiment, a method for fabricating an MOS structure comprises providing a semiconductor layer that is at least partially surrounded by an isolation region and that has an impurity-doped first portion. First and second MOS transistors are formed on and within the first portion. The transistors are substantially parallel and define a space therebetween. An insulating material is deposited overlying the first portion of the semiconductor layer and at least a portion of the isolation region. A contact is formed through the insulating material outside the space such that the contact is in electrical communication with the transistors.
摘要翻译：提供了具有远程触点的MOS结构和用于制造这种MOS结构的方法。在一个实施例中，一种用于制造MOS结构的方法包括提供半导体层，该半导体层至少部分地被隔离区包围，并且具有杂质掺杂的第一部分。第一和第二MOS晶体管形成在第一部分内部和第一部分内。晶体管基本上平行并且在它们之间限定了一个空间。沉积覆盖半导体层的第一部分和隔离区域的至少一部分的绝缘材料。通过空间外部的绝缘材料形成触点，使得触点与晶体管电连通。

3. 发明申请

US20130105944A1 METAL CAPACITOR DESIGN FOR IMPROVED RELIABILITY AND GOOD ELECTRICAL CONNECTION 有权
标题翻译：金属电容器设计，改善可靠性和良好的电气连接
公开(公告)号：US20130105944A1
公开(公告)日：2013-05-02
申请号：US13716693
申请日：2012-12-17
申请人： Jianhong ZHU , James F. Buller
发明人： Jianhong ZHU , James F. Buller
IPC分类号： H01L49/02
CPC分类号： H01L28/40 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A metal capacitor is formed with good conductivity for both nodes of the capacitor and improved reliability. An embodiment includes a first layer of alternating first and second metal lines, a second layer of alternating third and fourth metal lines, a dielectric layer between the first and second layers, and vias in the dielectric layer connecting the first and second metal lines with the third and fourth metal lines, respectively, wherein each metal line comprises alternating first segments having a first width and second segments having a second width, the first width being greater than the second width, each first segment lying adjacent to a second segment of an adjacent metal line, and only first segments of the metal lines overlapping the vias. The design enables the spacing between metal lines to be maintained, the spacing between via to metal to be increased, and via connection to be maintained for both nets, thereby improving the conductivity and reliability of the capacitor and maintaining capacitance density.
摘要翻译：形成对电容器的两个节点具有良好导电性的金属电容器，并提高可靠性。一个实施例包括交替的第一和第二金属线的第一层，交替的第三和第四金属线的第二层，第一和第二层之间的介电层，以及介电层中的通孔，将第一和第二金属线与第三和第四金属线，其中每个金属线包括具有第一宽度的交替的第一段和具有第二宽度的第二段，第一宽度大于第二宽度，每个第一段邻近相邻的第二段的第二段金属线，并且仅金属线的第一段与通孔重叠。该设计使得能够保持金属线之间的间距，通孔与金属之间的间隔增加，并且通过两个网络的连接来保持，从而提高电容器的导电性和可靠性并保持电容密度。

4. 发明公开

US20230193256A1 SYSTEM AND METHOD FOR GENE EDITING BY USING ENGINEERED CELL 审中-公开
公开(公告)号：US20230193256A1
公开(公告)日：2023-06-22
申请号：US17893132
申请日：2022-08-22
申请人： Jianhong Zhu , Huashan Hospital, Fudan University
发明人： Jianhong ZHU , Tianwen LI , Kezhu CHEN
IPC分类号： C12N15/11 , C12N9/22 , C07K14/705 , C12N15/86 , C12N5/0797
CPC分类号： C12N15/11 , C07K14/705 , C12N5/0623 , C12N9/22 , C12N15/86 , C12N2310/20 , C12N2502/086 , C12N2510/00 , C12N2740/15043
摘要： A system and method for gene editing by using an engineered cell are provided. The system includes the engineered cell embedded with a synthetic protein receptor and a target cell. The engineered cell contains a CRISPR/CasRx system and a sgRNA gene sequence. The synthetic protein receptor includes an extracellular target cell recognition domain, a native Notch core domain, an intramembranous hydrolyzable polypeptide and effectors. The extracellular target cell recognition domain can recognize antigen molecules on the target cell surface; and the effectors act as transcription factors for CasRx enzyme and sgRNAs. CasRx and gRNA are expressed in the engineered cell for gene editing to edit mRNA of the target cell. In this way, the application range of the engineered cell is expanded, the pertinence and specificity of gene editing are improved, the off-target effect is reduced, the collective non-specific reaction is reduced, and the safety of gene editing is improved.

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