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1. 发明授权

US5818751A Single-port SRAM with no read/write collisions 失效
标题翻译：单端口SRAM，无读/写冲突
公开(公告)号：US5818751A
公开(公告)日：1998-10-06
申请号：US925358
申请日：1997-09-08
申请人： Yung-Yuan Ho , Nang-Ping Tu , Jian-Yau Yih
发明人： Yung-Yuan Ho , Nang-Ping Tu , Jian-Yau Yih
IPC分类号： G11C11/419 , G11C11/00
CPC分类号： G11C11/419
摘要： A single-port SRAM with no read/write collisions. The present invention uses some X-axis and Y-axis control circuits to reduce the amounts of lines used in the structure of the present invention, but still maintains circuitry stability.
摘要翻译：单端口SRAM，无读/写冲突。本发明使用一些X轴和Y轴控制电路来减少在本发明的结构中使用的线的数量，但仍保持电路的稳定性。

2. 发明授权

US5831906A Read/write collison-free static random access memory 失效
标题翻译：读/写无碰撞静态随机存取存储器
公开(公告)号：US5831906A
公开(公告)日：1998-11-03
申请号：US827043
申请日：1997-03-25
申请人： Jian-Yau Yih , Nang-Ping Tu
发明人： Jian-Yau Yih , Nang-Ping Tu
IPC分类号： G11C11/413 , G11C7/22 , G11C8/12 , G11C11/418 , G11C11/419 , H01L21/8244 , H01L27/11 , G11C7/00
CPC分类号： G11C11/419 , G11C11/418 , G11C7/22 , G11C8/12
摘要： A read/write collision-free static random access memory which can perform read/write operations simultaneously without read/write collisions. The static random access memory includes a plurality of memory cells and its features are that the memory cells are divided into several memory banks wherein each bank has independent reading and writing paths. The number of memory cells for each memory bank can be determined by a specific length of memory cells between some memory cells undergoing reading operation and other memory cells undergoing writing operation, and by the reading speed of said reading operation and the writing speed of the writing operation, whereby the reading operation and the writing operation read and write to two different memory banks of the static random access memory at the same time such that read/write collisions can be prevented.
摘要翻译：无读/写冲突的读/写无冲突静态随机存取存储器，可同时执行读/写操作。静态随机存取存储器包括多个存储单元，其特征在于，存储器单元被分成若干存储体，其中每个存储体具有独立的读取和写入路径。每个存储体的存储单元的数量可以由经历读取操作的一些存储单元和正在进行写入操作的其他存储单元之间的存储单元的特定长度以及所述读取操作的读取速度和写入的写入速度来确定从而读取操作和写入操作同时读取和写入静态随机存取存储器的两个不同的存储体，从而可以防止读/写冲突。

3. 发明授权

US5729498A Reduced power consumption sram 失效
标题翻译：降低功耗sram
公开(公告)号：US5729498A
公开(公告)日：1998-03-17
申请号：US670376
申请日：1996-06-25
申请人： Jian-Yau Yih , Yung-Yuan Ho , Nang-Ping Tu , Jung-Dar Ho , Chien-Cheng Tu , Shaw-Jia Hor
发明人： Jian-Yau Yih , Yung-Yuan Ho , Nang-Ping Tu , Jung-Dar Ho , Chien-Cheng Tu , Shaw-Jia Hor
IPC分类号： G11C7/12 , G11C11/419 , G11C7/00 , G11C7/02 , G11C8/00 , G11C11/00
CPC分类号： G11C11/419 , G11C7/12
摘要： The continuing need for faster and denser SRAM memories places a constant increased demand on the power consumption of the memory devices. Much of the power consumption occurs during the pre-charge phase where it is common practice to bring up all pre-charge circuits at once and hold them active until the memory operations are complete. This invention describes a design where each pre-charge circuit connected to a group of memory cells through bit lines is activated at a separate time from the other pre-charge circuits. Thus each pre-charge circuit is active only during the time that useful work is being done with that portion of the memory. This reduces power consumption by not powering on circuits and precharging bit lines before they are actually needed.
摘要翻译：对于更快和更密集的SRAM存储器的持续需求对存储器件的功耗的需求不断增加。大部分功耗发生在预充电阶段，通常的做法是一次启动所有预充电电路并保持其活动直到存储器操作完成。本发明描述了一种设计，其中通过位线连接到一组存储器单元的每个预充电电路在与其它预充电电路分开的时间被激活。因此，每个预充电电路仅在与存储器的该部分进行有用的工作的时间有效。这在实际需要之前不通过电路供电和预充电位线来降低功耗。

4. 发明授权

US09275598B2 DAC architecture for LCD source driver 有权
标题翻译： DAC架构用于LCD源驱动
公开(公告)号：US09275598B2
公开(公告)日：2016-03-01
申请号：US12859888
申请日：2010-08-20
申请人： Nang-Ping Tu , Fu-Lung Hsueh , Mingo Liu
发明人： Nang-Ping Tu , Fu-Lung Hsueh , Mingo Liu
IPC分类号： G09G3/36 , H03M1/68 , H03M1/72 , H03M1/76 , H03M1/80
CPC分类号： G09G3/3696 , G09G3/3688 , G09G2310/027 , H03M1/687 , H03M1/72 , H03M1/76 , H03M1/804 , H03M1/806
摘要： A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a two-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, and a voltage selector. The voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.
摘要翻译：用于响应于M位数字输入代码输出模拟电压的两级数模转换器包括具有高参考电压输入节点的两位串行电荷再分配数模转换器，用于接收高电平参考电压和用于接收低参考电压的低参考电压输入节点，以及电压选择器。电压选择器将高参考电压和低参考电压设置为所选电平，这取决于至少一部分M位数字输入代码。

5. 发明授权

US08981979B2 Integrated circuits, liquid crystal display (LCD) drivers, and systems 有权
标题翻译：集成电路，液晶显示（LCD）驱动器和系统
公开(公告)号：US08981979B2
公开(公告)日：2015-03-17
申请号：US13466608
申请日：2012-05-08
申请人： Nang-Ping Tu , Fu-Lung Hsueh , Mingo Liu , I-Fey Wang
发明人： Nang-Ping Tu , Fu-Lung Hsueh , Mingo Liu , I-Fey Wang
IPC分类号： H03M1/66 , G09G3/36 , H03M1/76
CPC分类号： H03M1/66 , G09G3/3648 , G09G3/3685 , G09G2310/027 , G09G2310/0286 , G09G2310/0289 , G09G2310/0294 , H03M1/662 , H03M1/765
摘要： An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type DAC and at least one second channel type DAC. The integrated circuit includes a plurality of sample and hold (S/H) circuits. Each of the S/H circuits is coupled with the DAC circuit. The S/H circuits are capable of receiving signals from the DAC circuit and outputting the signals in parallel.
摘要翻译：集成电路包括数模转换器（DAC）电路，其包括至少一个第一通道类型DAC和至少一个第二通道类型DAC。集成电路包括多个采样和保持（S / H）电路。每个S / H电路与DAC电路耦合。 S / H电路能够从DAC电路接收信号并并行输出信号。

6. 发明授权

US09171518B2 Two-stage DAC achitecture for LCD source driver utilizing one-bit pipe DAC 有权
标题翻译：利用一位管道DAC的LCD驱动器的两级DAC架构
公开(公告)号：US09171518B2
公开(公告)日：2015-10-27
申请号：US12859892
申请日：2010-08-20
申请人： Nang-Ping Tu
发明人： Nang-Ping Tu
IPC分类号： G09G3/36 , H03M1/68 , H03M1/72 , H03M1/76 , H03M1/80
CPC分类号： G09G3/3696 , G09G3/3688 , G09G2310/027 , H03M1/687 , H03M1/72 , H03M1/76 , H03M1/804 , H03M1/806
摘要： A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, and a voltage selector. The voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.
摘要翻译：用于响应于M位数字输入代码输出模拟电压的两级数模转换器包括具有高参考电压输入节点的一位串行电荷再分配数模转换器，用于接收高电平参考电压和用于接收低参考电压的低参考电压输入节点，以及电压选择器。电压选择器将高参考电压和低参考电压设置为所选电平，这取决于至少一部分M位数字输入代码。

7. 发明授权

US08970639B2 Two-stage DAC architecture for LCD source driver utilizing one-bit serial charge redistribution DAC 有权
标题翻译：采用一位串行电荷再分配DAC的LCD源驱动器的两级DAC架构
公开(公告)号：US08970639B2
公开(公告)日：2015-03-03
申请号：US12859893
申请日：2010-08-20
申请人： Nang-Ping Tu
发明人： Nang-Ping Tu
IPC分类号： G09G5/10 , G09G3/36 , H03M1/68 , H03M1/66 , H03M1/72 , H03M1/76 , H03M1/80
CPC分类号： G09G3/3696 , G09G3/3688 , G09G2310/027 , H03M1/687 , H03M1/72 , H03M1/76 , H03M1/804 , H03M1/806
摘要： A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage. A voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.
摘要翻译：用于响应于M位数字输入代码输出模拟电压的两级数模转换器包括具有高参考电压输入节点的一位串行电荷再分配数模转换器，用于接收高电平参考电压和低参考电压输入节点，用于接收低参考电压。电压选择器根据M位数字输入代码的至少一部分将高参考电压和低参考电压设置为选定电平。

8. 发明授权

US08188898B2 Integrated circuits, liquid crystal display (LCD) drivers, and systems 有权
标题翻译：集成电路，液晶显示（LCD）驱动器和系统
公开(公告)号：US08188898B2
公开(公告)日：2012-05-29
申请号：US12762535
申请日：2010-04-19
申请人： Nang-Ping Tu , Fu-Long Hsueh , Mingo Liu , I-Fey Wang
发明人： Nang-Ping Tu , Fu-Long Hsueh , Mingo Liu , I-Fey Wang
IPC分类号： H03M1/66
CPC分类号： H03M1/66 , G09G3/3648 , G09G3/3685 , G09G2310/027 , G09G2310/0286 , G09G2310/0289 , G09G2310/0294 , H03M1/662 , H03M1/765
摘要： An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type DAC and at least one second channel type DAC. The integrated circuit includes a plurality of sample and hold (S/H) circuits. Each of the S/H circuits is coupled with one of the DAC circuit. The S/H circuits are capable of receiving signals from the DAC circuit and outputting the signals in parallel.
摘要翻译：集成电路包括数模转换器（DAC）电路，其包括至少一个第一通道类型DAC和至少一个第二通道类型DAC。集成电路包括多个采样和保持（S / H）电路。每个S / H电路与DAC电路中的一个耦合。 S / H电路能够从DAC电路接收信号并并行输出信号。

9. 发明授权

US5877717A D/A converter with a Gamma correction circuit 失效
标题翻译： D / A转换器，具有伽马校正电路
公开(公告)号：US5877717A
公开(公告)日：1999-03-02
申请号：US990443
申请日：1997-12-15
申请人： Nang-Ping Tu , Yong-Nian Rau , Chia-Yuan Chang
发明人： Nang-Ping Tu , Yong-Nian Rau , Chia-Yuan Chang
IPC分类号： H03M1/66 , H03M1/68 , H03M1/76 , H03M1/88
CPC分类号： H03M1/664 , H03M1/682 , H03M1/765
摘要： A D/A converter with a Gamma correction circuit according to the invention is designed for C-DAC which takes up much less space than the conventional R-DAC and 2-divided C-DAC. Therefore, this D/A converter has advantages of simple design and low cost. Furthermore, users can freely define the shape of a Gamma correction conversion curve to thereby widen application areas by adjusting terminal voltages.
摘要翻译：根据本发明的具有伽马校正电路的D / A转换器被设计用于C-DAC，其占用比常规R-DAC和2分频C-DAC少得多的空间。因此，该D / A转换器具有设计简单，成本低的优点。此外，用户可以自由地定义伽马校正转换曲线的形状，从而通过调整端子电压来扩大应用领域。

10. 发明授权

US4978870A CMOS digital level shifter circuit 失效
标题翻译： CMOS数字电平转换电路
公开(公告)号：US4978870A
公开(公告)日：1990-12-18
申请号：US382136
申请日：1989-07-19
申请人： Ming-Daw Chen , Nang-Ping Tu
发明人： Ming-Daw Chen , Nang-Ping Tu
IPC分类号： H03K19/00 , H03K3/356
CPC分类号： H03K3/356104
摘要： The apparatus of the present invention is a CMOS digital level shifter circuit which includes an inverter connected to a voltage generator. The voltage generator comprises an NMOS source follower connected to a directional switching element and a voltage regulating capacitor. The level shifter further includes a latch energized by the same voltage supply energizing the voltage generator. Each branch of the latch has a complementary MOS transistor pair with common gates connected to the output of the inverter and to the input signal respectively. Each complementary transistor pair is connected to the voltage supply by a latch transistor whose gate is cross-connected to the complementary transistor pair of the other branch. Whenever the one transistor in each complementary pair which is connected to ground is on, the latch transistor is latched off by the complementary transistor pair in the other branch after each voltage transition by the input signal, thereby reducing or eliminating DC power consumption, while requiring only a single voltage supply.
摘要翻译：本发明的装置是CMOS数字电平转换电路，其包括连接到电压发生器的反相器。电压发生器包括连接到方向开关元件和电压调节电容器的NMOS源极跟随器。电平移位器还包括由相同的电压源供电的闩锁，该电压为电压发生器通电。锁存器的每个分支具有互补MOS晶体管对，其公共栅极分别连接到反相器的输出端和输入信号。每个互补晶体管对通过其栅极交叉连接到另一个分支的互补晶体管对的锁存晶体管连接到电压源。每当连接到地的互补对中的一个晶体管导通时，在通过输入信号的每个电压转换之后，锁存晶体管在另一分支中的互补晶体管对被锁存，从而减少或消除直流功耗，同时要求只有一个电压供应。

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