专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06747857B1 Clamping circuit for stacked NMOS ESD protection 有权
标题翻译：用于堆叠NMOS ESD保护的钳位电路
公开(公告)号：US06747857B1
公开(公告)日：2004-06-08
申请号：US10062706
申请日：2002-02-01
申请人： Jian-Hsing Lee , Hung-Der Su , Jiaw-Ren Shih
发明人： Jian-Hsing Lee , Hung-Der Su , Jiaw-Ren Shih
IPC分类号： H02H900
CPC分类号： H03K17/0822 , H01L27/0266 , H03K17/6872
摘要： A novel device and process is described for an ESD protection device for complimentary cascaded NMOS output circuit strings. The invention consists of a clamping NMOS with gate connected to the input or output pad through a diode and connected to ground through a resistor. The clamping device drain is connected to the signal gate of the active output NMOS and the clamping device source is connected to ground. An ESD event causes the diode to go into breakdown mode and the conduction current across the resistor places a positive voltage on the clamping device gate turning the clamping device on. This clamps the active NMOS signal gate to ground assuring that the output NMOS remains in an off condition during the ESD event. This prevents any damage due to high current flow through the active, or used output inverter string.
摘要翻译：对于用于互补级联的NMOS输出电路串的ESD保护器件描述了一种新颖的器件和工艺。本发明包括一个钳位NMOS，其栅极通过二极管连接到输入或输出焊盘，并通过电阻器连接到地。钳位装置漏极连接到有源输出NMOS的信号栅极，钳位装置源连接到地。 ESD事件导致二极管进入击穿模式，并且电阻两端的导通电流在夹紧装置门上施加正电压，使夹紧装置打开。这将有源NMOS信号栅极钳位到地，确保在ESD事件期间输出NMOS保持关断状态。这可以防止由于高电流流过有源或使用的输出逆变器串造成的任何损坏。

2. 发明授权

US08288822B2 ESD protection structures on SOI substrates 有权
标题翻译： SOI衬底上的ESD保护结构
公开(公告)号：US08288822B2
公开(公告)日：2012-10-16
申请号：US13172555
申请日：2011-06-29
申请人： Jiaw-Ren Shih , Jian-Hsing Lee
发明人： Jiaw-Ren Shih , Jian-Hsing Lee
IPC分类号： H01L27/06
CPC分类号： H01L27/0259 , H01L27/1203
摘要： An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.
摘要翻译：静电放电（ESD）保护电路包括埋氧层; 掩埋氧化物层上的半导体层; 以及第一和第二MOS器件。第一MOS器件包括半导体层上的第一栅极; 第一阱区，具有位于第一栅极下面的部分; 以及半导体层中的第一源极区域和第一漏极区域。第二MOS器件包括半导体层上的第二栅极; 以及具有位于第一栅极下方的部分的第二阱区。第二阱区连接到放电节点。第一阱区域通过第二阱区域连接到放电节点，并且不直接连接到放电节点。第二MOS器件还包括半导体层中的第二源极区域和第二漏极区域并与第二阱区域邻接。

3. 发明申请

US20110254091A1 ESD Protection Structures on SOI Substrates 有权
标题翻译： SOI衬底上的ESD保护结构
公开(公告)号：US20110254091A1
公开(公告)日：2011-10-20
申请号：US13172555
申请日：2011-06-29
申请人： Jiaw-Ren Shih , Jian-Hsing Lee
发明人： Jiaw-Ren Shih , Jian-Hsing Lee
IPC分类号： H01L27/12
CPC分类号： H01L27/0259 , H01L27/1203
摘要： An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.
摘要翻译：静电放电（ESD）保护电路包括埋氧层; 掩埋氧化物层上的半导体层; 以及第一和第二MOS器件。第一MOS器件包括半导体层上的第一栅极; 第一阱区，具有位于第一栅极下面的部分; 以及半导体层中的第一源极区域和第一漏极区域。第二MOS器件包括半导体层上的第二栅极; 以及具有位于第一栅极下方的部分的第二阱区。第二阱区连接到放电节点。第一阱区域通过第二阱区域连接到放电节点，并且不直接连接到放电节点。第二MOS器件还包括半导体层中的第二源极区域和第二漏极区域并与第二阱区域邻接。

4. 发明申请

US20050176195A1 Decoupling capacitor 有权
公开(公告)号：US20050176195A1
公开(公告)日：2005-08-11
申请号：US11072014
申请日：2005-03-04
申请人： Jiaw-Ren Shih , Jian-Hsing Lee , Shui-Hung Chen
发明人： Jiaw-Ren Shih , Jian-Hsing Lee , Shui-Hung Chen
IPC分类号： H01G4/228 , H01G4/35 , H01L21/8234 , H01L23/60 , H02H9/00
CPC分类号： H01L27/0251
摘要： A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.

5. 发明授权

US06614078B2 Highly latchup-immune CMOS I/O structures 有权
公开(公告)号：US06614078B2
公开(公告)日：2003-09-02
申请号：US10147272
申请日：2002-05-16
申请人： Jian-Hsing Lee , Jiaw-Ren Shih , Shui-Hung Chen , Ping-Lung Liao
发明人： Jian-Hsing Lee , Jiaw-Ren Shih , Shui-Hung Chen , Ping-Lung Liao
IPC分类号： H01L2976
CPC分类号： H01L21/823878 , H01L27/0921
摘要： CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively. In either of the two preferred embodiments the reduced shunt resistances prevent the forward biasing of the parasitic bipolar transistors of the SCR, thus insuring that the holding voltage is larger than the supply voltage.

6. 发明授权

US06420221B1 Method of manufacturing a highly latchup-immune CMOS I/O structure 有权
标题翻译：制造高度闭锁免疫CMOS I / O结构的方法
公开(公告)号：US06420221B1
公开(公告)日：2002-07-16
申请号：US09507646
申请日：2000-02-22
申请人： Jian-Hsing Lee , Jiaw-Ren Shih , Shui-hung Chen , Ping-Lung Liao
发明人： Jian-Hsing Lee , Jiaw-Ren Shih , Shui-hung Chen , Ping-Lung Liao
IPC分类号： H01L218238
CPC分类号： H01L21/823878 , H01L27/0921
摘要： CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively. In either of the two preferred embodiments the reduced shunt resistances prevent the forward biasing of the parasitic bipolar transistors of the SCR, thus insuring that the holding voltage is larger than the supply voltage.
摘要翻译：通过将p +和n +扩散保护环分别插入到半导体衬底的NMOS和PMOS源极侧中，分别描述了通过插入 - 免疫的CMOS I / O结构。 P +扩散保护环围绕各个n沟道晶体管，n +扩散保护环围绕着单独的p沟道晶体管。连接到电源的这些保护环通过p型衬底到p +保护环或n阱到n +保护环，降低了与CMOS结构通常相关的寄生SCR的分流电阻。在第二优选实施例中，将深p +注入植入到p +保护环或p阱拾取器中以降低寄生SCR的分流电阻。与第一优选实施例的保护环相同的n +和p +保护环分别连接到正和负电压源。在两个优选实施例中的任一个中，减小的分流电阻防止SCR的寄生双极晶体管的正向偏置，从而确保保持电压大于电源电压。

7. 发明授权

US07518192B2 Asymmetrical layout structure for ESD protection 有权
标题翻译： ESD保护的非对称布局结构
公开(公告)号：US07518192B2
公开(公告)日：2009-04-14
申请号：US10985532
申请日：2004-11-10
申请人： Kuo-Feng Yu , Jian-Hsing Lee , Jiaw-Ren Shih , Fu Chin Yang
发明人： Kuo-Feng Yu , Jian-Hsing Lee , Jiaw-Ren Shih , Fu Chin Yang
IPC分类号： H01L23/62
CPC分类号： H01L21/76816 , H01L27/0274 , H01L29/78
摘要： A semiconductor structure for electrostatic discharge protection is presented. The semiconductor structure comprises a grounded gate nMOS (GGNMOS) having a substrate, a gate electrode, a source region and a drain region. A plurality of contact plugs is formed on the source and drain side. A plurality of first level vias is electrically coupled to the GGNMOS and has a substantially asymmetrical layout in the source and drain regions. A second level via(s) re-routes the ESD current to the desired first level vias. The uniformity of the current flow in the GGNMOS is improved.
摘要翻译：提出了一种用于静电放电保护的半导体结构。半导体结构包括具有衬底，栅极电极，源极区域和漏极区域的接地栅极nMOS（GGNMOS）。在源极和漏极侧形成多个接触插塞。多个第一级通孔电耦合到GGNMOS并且在源极和漏极区域中具有基本不对称的布局。第二级通过将ESD电流重新路由到期望的第一级通孔。 GGNMOS中电流的均匀性得到改善。

8. 发明申请

US20080137244A1 Electrostatic discharge protection circuit 审中-公开
标题翻译：静电放电保护电路
公开(公告)号：US20080137244A1
公开(公告)日：2008-06-12
申请号：US11637108
申请日：2006-12-12
申请人： Kuo-Feng Yo , Jian-Hsing Lee , Jiaw-Ren Shih , Fu-Chin Yang
发明人： Kuo-Feng Yo , Jian-Hsing Lee , Jiaw-Ren Shih , Fu-Chin Yang
IPC分类号： H02H9/00
CPC分类号： H01L27/0262
摘要： An electrostatic discharge (ESD) protection circuit. The ESD protection circuit comprises a silicon controlled rectifier (SCR) device and a metal-oxide-semiconductor (MOS) triggering device. The SCR device has a cathode connected to a first fixed potential and an anode. The MOS triggering device has a gate and a source connected to the first fixed potential and a drain connected to the anode. In addition, the MOS triggering device is not physically disposed in the SCR device.
摘要翻译：静电放电（ESD）保护电路。 ESD保护电路包括可控硅整流器（SCR）器件和金属氧化物半导体（MOS）触发器件。 SCR器件具有连接到第一固定电位和阳极的阴极。 MOS触发装置具有连接到第一固定电位的栅极和源极以及连接到阳极的漏极。此外，MOS触发装置没有物理地设置在SCR装置中。

9. 发明授权

US06459127B1 Uniform current distribution SCR device for high voltage ESD protection 有权
标题翻译：均匀电流分配用于高压ESD保护的SCR器件
公开(公告)号：US06459127B1
公开(公告)日：2002-10-01
申请号：US10043793
申请日：2002-01-14
申请人： Jian-Hsing Lee , Kuo-Chio Liu , Bing-Lung Liao , Jiaw-Ren Shih
发明人： Jian-Hsing Lee , Kuo-Chio Liu , Bing-Lung Liao , Jiaw-Ren Shih
IPC分类号： H01L2362
CPC分类号： H01L27/0266
摘要： NMOS transistors for a high voltage process are protected from electrostatic discharge (ESD) by parasitic SCRs, where the two NMOS transistors and the two SCRs are designed to be in a completely symmetrical arrangement so that the currents in the components of the SCRs are completely uniform. This symmetry is achieved by adding a p+ diffusion to the source of one of the NMOS transistors. The added p+ diffusion guarantees that the resistance seen by both SCRs is identical. This insures even current distribution between both SCRs and thereby improves the high voltage characteristics of the ESD device.
摘要翻译：用于高电压工艺的NMOS晶体管通过寄生SCR防止静电放电（ESD），其中两个NMOS晶体管和两个SCR被设计为完全对称的布置，使得SCR的部件中的电流是完全均匀的。该对称性是通过向NMOS晶体管之一的源极添加p +扩散来实现的。添加的p +扩散保证两个SCR看到的电阻是相同的。这确保了两个SCR之间的均匀电流分布，从而改善了ESD器件的高电压特性。

10. 发明授权

US06437408B1 Plasma damage protection cell using floating N/P/N and P/N/P structure 有权
标题翻译：使用浮动N / P / N和P / N / P结构的等离子体损伤保护电池
公开(公告)号：US06437408B1
公开(公告)日：2002-08-20
申请号：US09904146
申请日：2001-07-13
申请人： Jiaw-Ren Shih , Shui-Hung Shen , Jian-Hsing Lee , Chrong Jung Lin
发明人： Jiaw-Ren Shih , Shui-Hung Shen , Jian-Hsing Lee , Chrong Jung Lin
IPC分类号： H01L2100
CPC分类号： H01L21/28123
摘要： A plasma damage protection cell using floating N/P/N and P/N/P structure, and a method to form the same are disclosed. Floating structures of the protection cell and the floating gates for the MOS devices are formed simultaneously on a semiconductor substrate having shallow trench isolation. The floating structures are implanted separately to form the N/P/N and P/N/P bipolar base, emitter and collector regions while the source/drain of the respective NMOS and PMOS devices are implanted with appropriate sequencing. The floating structures are connected to the substrate with appropriate polarity to provide protection at low leakage current levels and with tunable punch-through voltages.
摘要翻译：公开了使用浮动N / P / N和P / N / P结构的等离子体损伤保护单元及其形成方法。保护电池的浮动结构和用于MOS器件的浮置栅极同时形成在具有浅沟槽隔离的半导体衬底上。分别注入浮动结构以形成N / P / N和P / N / P双极基极，发射极和集电极区域，同时以适当的顺序植入各个NMOS和PMOS器件的源极/漏极。浮动结构以适当的极性连接到基板，以在低泄漏电流水平和可调穿通电压下提供保护。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式