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1. 发明申请

US20050083735A1 Behavior based programming of non-volatile memory 有权
标题翻译：非易失性存储器的基于行为的编程
公开(公告)号：US20050083735A1
公开(公告)日：2005-04-21
申请号：US10689333
申请日：2003-10-20
申请人： Jian Chen , Jeffrey Lutze , Yan Li , Daniel Guterman , Tomoharu Tanaka
发明人： Jian Chen , Jeffrey Lutze , Yan Li , Daniel Guterman , Tomoharu Tanaka
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/12
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C16/3459
摘要： The process for programming a set of memory cells is improved by adapting the programming process based on behavior of the memory cells. For example, a set of program pulses is applied to the word line for a set of flash memory cells. A determination is made as to which memory cells are easier to program and which memory cells are harder to program. Bit line voltages (or other parameters) can be adjusted based on the determination of which memory cells are easier to program and which memory cells are harder to program. The programming process will then continue with the adjusted bit line voltages (or other parameters).
摘要翻译：通过基于存储器单元的行为调整编程过程来改进用于对一组存储器单元进行编程的过程。例如，一组编程脉冲被施加到一组闪存单元的字线。确定哪些存储器单元更容易编程，哪些存储器单元难以编程。可以基于确定哪些存储器单元更容易编程以及哪些存储器单元难以编程来调整位线电压（或其他参数）。然后，编程过程将继续调整的位线电压（或其他参数）。

2. 发明申请

US20070121383A1 BEHAVIOR BASED PROGRAMMING OF NON-VOLATILE MEMORY 有权
标题翻译：基于行为的非易失性存储器编程
公开(公告)号：US20070121383A1
公开(公告)日：2007-05-31
申请号：US11624052
申请日：2007-01-17
申请人： Jian Chen , Jeffrey Lutze , Yan Li , Daniel Guterman , Tomoharu Tanaka
发明人： Jian Chen , Jeffrey Lutze , Yan Li , Daniel Guterman , Tomoharu Tanaka
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C16/3459
摘要： The process for programming a set of memory cells is improved by adapting the programming process based on behavior of the memory cells. For example, a set of program pulses is applied to the word line for a set of flash memory cells. A determination is made as to which memory cells are easier to program and which memory cells are harder to program. Bit line voltages (or other parameters) can be adjusted based on the determination of which memory cells are easier to program and which memory cells are harder to program. The programming process will then continue with the adjusted bit line voltages (or other parameters).
摘要翻译：通过基于存储器单元的行为调整编程过程来改进用于对一组存储器单元进行编程的过程。例如，一组编程脉冲被施加到一组闪存单元的字线。确定哪些存储器单元更容易编程，哪些存储器单元难以编程。可以基于确定哪些存储器单元更容易编程以及哪些存储器单元难以编程来调整位线电压（或其他参数）。然后，编程过程将继续调整的位线电压（或其他参数）。

3. 发明申请

US20050057968A1 Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance 有权
标题翻译：用于识别具有差的亚阈值斜率或弱跨导的非易失性存储元件的方法
公开(公告)号：US20050057968A1
公开(公告)日：2005-03-17
申请号：US10665685
申请日：2003-09-17
申请人： Jeffrey Lutze , Jian Chen , Yan Li , Kazunori Kanebako , Tomoharu Tanaka
发明人： Jeffrey Lutze , Jian Chen , Yan Li , Kazunori Kanebako , Tomoharu Tanaka
IPC分类号： G01R31/28 , G11C16/02 , G11C16/04 , G11C16/34 , G11C29/50 , G11C29/56 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3495 , G11C16/04 , G11C16/349 , G11C29/50 , G11C29/50004
摘要： The present invention presents a number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behavior of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behavior by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.
摘要翻译：本发明提出了用于鉴别具有差的亚阈值斜率和降低的跨导的细胞的许多方法。第一组技术集中在通过循环单元对劣化的存储元件的差的亚阈值行为进行编程，然后将它们编程到高于基态的状态，并以低于该状态的阈值电压的控制栅极电压读取它们，以查看它们是否仍然进行。第二组实施例通过利用远高于阈值电压的控制栅极电压读取编程单元来侧重于弱跨导行为。第三组实施例改变存储元件的源极 - 漏极区域处的电压电平。在偏置条件下的这种偏移下，良好存储元件的电流 - 电压曲线相对稳定，而退化元件表现出较大的偏移。偏移量可以用来区分好的元素和坏的元素。

4. 发明申请

US20080037319A1 Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance 有权
标题翻译：用于识别具有差的亚阈值斜率或弱跨导的非易失性存储元件的方法
公开(公告)号：US20080037319A1
公开(公告)日：2008-02-14
申请号：US11389557
申请日：2006-03-23
申请人： Jeffrey Lutze , Jian Chen , Yan Li , Kazunori Kanebako , Tomoharu Tanaka
发明人： Jeffrey Lutze , Jian Chen , Yan Li , Kazunori Kanebako , Tomoharu Tanaka
IPC分类号： G11C11/34
CPC分类号： G11C16/3495 , G11C16/04 , G11C16/349 , G11C29/50 , G11C29/50004
摘要： The present invention presents a number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behavior of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behavior by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.
摘要翻译：本发明提出了用于鉴别具有差的亚阈值斜率和降低的跨导的细胞的许多方法。第一组技术集中在通过循环单元对劣化的存储元件的差的亚阈值行为进行编程，然后将它们编程到高于基态的状态，并以低于该状态的阈值电压的控制栅极电压读取它们，以查看它们是否仍然进行。第二组实施例通过利用远高于阈值电压的控制栅极电压读取编程单元来侧重于弱跨导行为。第三组实施例改变存储元件的源极 - 漏极区域处的电压电平。在偏置条件下的这种偏移下，良好存储元件的电流 - 电压曲线相对稳定，而退化元件表现出较大的偏移。偏移量可以用来区分好的元素和坏的元素。

5. 发明申请

US20050207222A1 Detecting over programmed memory 有权
公开(公告)号：US20050207222A1
公开(公告)日：2005-09-22
申请号：US11124709
申请日：2005-05-09
申请人： Jian Chen , Yan Li , Jeffrey Lutze
发明人： Jian Chen , Yan Li , Jeffrey Lutze
IPC分类号： G11C11/56 , G11C16/04 , G11C16/34
CPC分类号： G11C16/3463 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3454 , G11C16/3459
摘要： In a non-volatile semiconductor memory system (or other type of memory system), a memory cell is programmed by changing the threshold voltage of that memory cell. Because of variations in the programming speeds of different memory cells in the system, the possibility exists that some memory cells will be over programmed. That is, in one example, the threshold voltage will be moved past the intended value or range of values. The present invention includes determining whether the memory cells are over programmed.

6. 发明申请

US20050024943A1 Detecting over programmed memory after further programming 有权
标题翻译：进一步编程后检测编程存储器
公开(公告)号：US20050024943A1
公开(公告)日：2005-02-03
申请号：US10628962
申请日：2003-07-29
申请人： Jian Chen , Yan Li , Jeffrey Lutze
发明人： Jian Chen , Yan Li , Jeffrey Lutze
IPC分类号： G11C16/34 , G11C11/34
CPC分类号： G11C16/3404 , G11C16/3454
摘要： In a non-volatile semiconductor memory system (or other type of memory system), a memory cell is programmed by changing the threshold voltage of that memory cell. Because of variations in the programming speeds of different memory cells in the system, the possibility exists that some memory cells will be over programmed. That is, in one example, the threshold voltage will be moved past the intended value or range of values. The present invention includes determining whether the memory cells are over programmed.
摘要翻译：在非易失性半导体存储器系统（或其他类型的存储器系统）中，通过改变该存储器单元的阈值电压对存储器单元进行编程。由于系统中不同存储器单元的编程速度的变化，存在一些存储器单元将被过度编程的可能性。也就是说，在一个示例中，阈值电压将被移动超过预期值或值的范围。本发明包括确定存储器单元是否被过度编程。

7. 发明申请

US20050024939A1 Detecting over programmed memory 有权
标题翻译：检测编程内存
公开(公告)号：US20050024939A1
公开(公告)日：2005-02-03
申请号：US10629068
申请日：2003-07-29
申请人： Jian Chen , Yan Li , Jeffrey Lutze
发明人： Jian Chen , Yan Li , Jeffrey Lutze
IPC分类号： G11C11/56 , G11C16/04 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3463 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3454 , G11C16/3459
摘要： In a non-volatile semiconductor memory system (or other type of memory system), a memory cell is programmed by changing the threshold voltage of that memory cell. Because of variations in the programming speeds of different memory cells in the system, the possibility exists that some memory cells will be over programmed. That is, in one example, the threshold voltage will be moved past the intended value or range of values. The present invention includes determining whether the memory cells are over programmed.
摘要翻译：在非易失性半导体存储器系统（或其他类型的存储器系统）中，通过改变该存储器单元的阈值电压对存储器单元进行编程。由于系统中不同存储器单元的编程速度的变化，存在一些存储器单元将被过度编程的可能性。也就是说，在一个示例中，阈值电压将被移动超过预期值或值的范围。本发明包括确定存储器单元是否被过度编程。

8. 发明申请

US20050128810A1 Self-boosting technique 失效
标题翻译：自我增强技术
公开(公告)号：US20050128810A1
公开(公告)日：2005-06-16
申请号：US11049802
申请日：2005-02-03
申请人： Jeffrey Lutze , Jian Chen , Yan Li , Masaaki Higashitani
发明人： Jeffrey Lutze , Jian Chen , Yan Li , Masaaki Higashitani
IPC分类号： G11C11/34 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/34
CPC分类号： G11C16/3418 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3454
摘要： A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source side of the NAND string during the programming process. One exemplar implementation includes applying a voltage (e.g. Vdd) to the source contact and turning on the source side select transistor for the NAND sting corresponding to the cell being inhibited. Another implementation includes applying a pre-charging voltage to the unselected word lines of the NAND string corresponding to the cell being inhibited prior to applying the program voltage.
摘要翻译：以避免程序干扰的方式编程非易失性半导体存储器系统（或其他类型的存储器系统）。在包括使用NAND架构的闪存系统的一个实施例中，通过在编程处理期间增加NAND串的源侧的沟道电位来避免程序干扰。一个示例性实施方案包括将电压（例如Vdd）施加到源极触点，并且接通源抑制对应的单元的NAND极的源极侧选择晶体管。另一种实施方案包括在施加编程电压之前，将预充电电压施加到对应于被禁止的单元的NAND串的未选择字线。

9. 发明申请

US20070086251A1 APPARATUS FOR CONTROLLED PROGRAMMING OF NON-VOLATILE MEMORY EXHIBITING BIT LINE COUPLING 有权
标题翻译：用于非挥发性记忆展示位线耦合的控制编程设备
公开(公告)号：US20070086251A1
公开(公告)日：2007-04-19
申请号：US11251458
申请日：2005-10-14
申请人： Jeffrey Lutze , Yan Li , Siu Chan
发明人： Jeffrey Lutze , Yan Li , Siu Chan
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C7/12 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C16/3454 , G11C2211/5621
摘要： The effects of bit line-to-bit line coupling in a non-volatile memory are addressed. An inhibit voltage is applied on a bit line of a storage element to be programmed to inhibit programming during a portion of a program voltage. The inhibit voltage is subsequently removed during the program voltage to allow programming to occur. Due to the proximity of bit lines, the change in the bit line voltage is coupled to a neighboring unselected bit line, reducing the neighboring bit line voltage to a level which might be sufficient to open a select gate and discharge a boost voltage. To prevent this, the select gate voltage is temporarily adjusted during the change in the bit line voltage to ensure that the biasing of the select gate on the unselected bit line is not sufficient to open the select gate.
摘要翻译：解决位线对位线耦合在非易失性存储器中的影响。在编程的存储元件的位线上施加禁止电压，以在编程电压的一部分期间禁止编程。随后在编程电压期间去除抑制电压以允许编程发生。由于位线的接近，位线电压的变化被耦合到相邻的未选位线，将相邻的位线电压减小到可能足以打开选择栅极并放电升压电压的电平。为了防止这种情况，在位线电压变化期间临时调整选择栅极电压，以确保未选定位线上的选择栅极的偏置不足以打开选择栅极。

10. 发明授权

US07254071B2 Flash memory devices with trimmed analog voltages 有权
标题翻译：具有微调模拟电压的闪存设备
公开(公告)号：US07254071B2
公开(公告)日：2007-08-07
申请号：US11332567
申请日：2006-01-12
申请人： Loc Tu , Jeffrey Lutze , Jun Wan , Jian Chen
发明人： Loc Tu , Jeffrey Lutze , Jun Wan , Jian Chen
IPC分类号： G11C29/00
CPC分类号： G11C16/0483 , G11C7/16 , G11C11/5628 , G11C16/04 , G11C16/12 , G11C16/3454 , G11C16/3459 , G11C27/005 , G11C29/028 , G11C29/48 , G11C29/50 , G11C29/50004 , G11C2029/5004 , G11C2211/5621 , G11C2211/5634
摘要： A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell so that the threshold voltage of the cell can be sensed. A digital-to-analog converter (DAC) use for programming and a second read/verify DAC apply varying analog voltages and are sequentially used to verify the programming of an associated set of memory cells in this special test mode, with the DAC input values that provide the closest result selected for use in normal operation. These DAC's are dependent on the value of a reference source that my also be trimmed.
摘要翻译：公开了一种多电平单元（MLC）类型的闪速存储器件，其中读取和编程操作中的控制栅极电压和带隙基准电压源可从外部端子进行调节。在特殊测试模式中，可以将控制栅极电压施加到所选择的编程存储单元，从而可以感测单元的阈值电压。用于编程的数/模转换器（DAC）和第二读/验用DAC应用变化的模拟电压，并且在该特殊测试模式下依次用于验证相关联的存储器单元的编程，DAC输入值它提供了选择用于正常操作的最接近的结果。这些DAC取决于我也被修剪的参考源的值。

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