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    • 2. 发明申请
    • METHOD FOR CONTROLLED PROGRAMMING OF NON-VOLATILE MEMORY EXHIBITING BIT LINE COUPLING
    • 非挥发性记忆展示位线耦合的控制编程方法
    • US20070086247A1
    • 2007-04-19
    • US11250735
    • 2005-10-14
    • Jeffrey LutzeYan LiSiu Chan
    • Jeffrey LutzeYan LiSiu Chan
    • G11C16/04
    • G11C16/3418G11C16/3427
    • The effects of bit line-to-bit line coupling in a non-volatile memory are addressed. An inhibit voltage is applied on a bit line of a storage element to be programmed to inhibit programming during a portion of a program voltage. The inhibit voltage is subsequently removed during the program voltage to allow programming to occur. Due to the proximity of bit lines, the change in the bit line voltage is coupled to a neighboring unselected bit line, reducing the neighboring bit line voltage to a level which might be sufficient to open a select gate and discharge a boost voltage. To prevent this, the select gate voltage is temporarily adjusted during the change in the bit line voltage to ensure that the biasing of the select gate on the unselected bit line is not sufficient to open the select gate.
    • 解决位线对位线耦合在非易失性存储器中的影响。 在编程的存储元件的位线上施加禁止电压,以在编程电压的一部分期间禁止编程。 随后在编程电压期间去除抑制电压以允许编程发生。 由于位线的接近,位线电压的变化被耦合到相邻的未选位线,将相邻的位线电压减小到可能足以打开选择栅极并放电升压电压的电平。 为了防止这种情况,在位线电压变化期间临时调整选择栅极电压,以确保未选定位线上的选择栅极的偏置不足以打开选择栅极。
    • 10. 发明申请
    • Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance
    • 用于识别具有差的亚阈值斜率或弱跨导的非易失性存储元件的方法
    • US20080037319A1
    • 2008-02-14
    • US11389557
    • 2006-03-23
    • Jeffrey LutzeJian ChenYan LiKazunori KanebakoTomoharu Tanaka
    • Jeffrey LutzeJian ChenYan LiKazunori KanebakoTomoharu Tanaka
    • G11C11/34
    • G11C16/3495G11C16/04G11C16/349G11C29/50G11C29/50004
    • The present invention presents a number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behavior of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behavior by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.
    • 本发明提出了用于鉴别具有差的亚阈值斜率和降低的跨导的细胞的许多方法。 第一组技术集中在通过循环单元对劣化的存储元件的差的亚阈值行为进行编程,然后将它们编程到高于基态的状态,并以低于该状态的阈值电压的控制栅极电压读取它们,以查看它们是否仍然 进行。 第二组实施例通过利用远高于阈值电压的控制栅极电压读取编程单元来侧重于弱跨导行为。 第三组实施例改变存储元件的源极 - 漏极区域处的电压电平。 在偏置条件下的这种偏移下,良好存储元件的电流 - 电压曲线相对稳定,而退化元件表现出较大的偏移。 偏移量可以用来区分好的元素和坏的元素。