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1. 发明申请

US20080287071A1 EXPANDABLE WIRELESS TRANSCEIVER 有权
标题翻译：可扩展的无线收发器
公开(公告)号：US20080287071A1
公开(公告)日：2008-11-20
申请号：US11778853
申请日：2007-07-17
申请人： Jiahn-Rong Gau , Ching-Cheng Huang , Cheng-Hsiung Hsu , Tzu-Ping Lin , Chen-Chia Huang
发明人： Jiahn-Rong Gau , Ching-Cheng Huang , Cheng-Hsiung Hsu , Tzu-Ping Lin , Chen-Chia Huang
IPC分类号： H04B1/38
CPC分类号： H04B1/48
摘要： An expandable wireless transceiver is provided. The expandable wireless transceiver includes an antenna, a receiver, a transmitter and a switch connector. The antenna detects an electromagnetic signal in surrounding space and receives a signal with a first central frequency according to the detection result. The receiver receives the signal based on the detection result of the antenna. The transmitter outputs a radio-frequency signal. A third connection terminal of the switch connector provides a connective path to an expansion antenna. According to the coupling condition of the third connection terminal, the switch connector delivers the radio-frequency signal to its second connection terminal or third connection terminal. Thus, the radio-frequency signal with a second central frequency is transmitted to surrounding space through the antenna or the expansion antenna, wherein the second central frequency and the first central frequency are both in a specific band.
摘要翻译：提供可扩展的无线收发器。可扩展无线收发器包括天线，接收器，发射器和开关连接器。天线检测周围空间的电磁信号，并根据检测结果接收具有第一中心频率的信号。接收机根据天线的检测结果接收信号。发射机输出射频信号。开关连接器的第三连接端子提供到扩展天线的连接路径。根据第三连接端子的耦合条件，开关连接器将射频信号传送到其第二连接端子或第三连接端子。因此，具有第二中心频率的射频信号通过天线或扩展天线发送到周围空间，其中第二中心频率和第一中心频率均处于特定频带。

2. 发明授权

US07796955B2 Expandable wireless transceiver 有权
标题翻译：可扩展无线收发器
公开(公告)号：US07796955B2
公开(公告)日：2010-09-14
申请号：US11778853
申请日：2007-07-17
申请人： Jiahn-Rong Gau , Ching-Cheng Huang , Cheng-Hsiung Hsu , Tzu-Ping Lin , Chen-Chia Huang
发明人： Jiahn-Rong Gau , Ching-Cheng Huang , Cheng-Hsiung Hsu , Tzu-Ping Lin , Chen-Chia Huang
IPC分类号： H04B1/38
CPC分类号： H04B1/48
摘要： An expandable wireless transceiver is provided. The expandable wireless transceiver includes an antenna, a receiver, a transmitter and a switch connector. The antenna detects an electromagnetic signal in surrounding space and receives a signal with a first central frequency according to the detection result. The receiver receives the signal based on the detection result of the antenna. The transmitter outputs a radio-frequency signal. A third connection terminal of the switch connector provides a connective path to an expansion antenna. According to the coupling condition of the third connection terminal, the switch connector delivers the radio-frequency signal to its second connection terminal or third connection terminal. Thus, the radio-frequency signal with a second central frequency is transmitted to surrounding space through the antenna or the expansion antenna, wherein the second central frequency and the first central frequency are both in a specific band.
摘要翻译：提供可扩展的无线收发器。可扩展无线收发器包括天线，接收器，发射器和开关连接器。天线检测周围空间的电磁信号，并根据检测结果接收具有第一中心频率的信号。接收机根据天线的检测结果接收信号。发射机输出射频信号。开关连接器的第三连接端子提供到扩展天线的连接路径。根据第三连接端子的耦合条件，开关连接器将射频信号传送到其第二连接端子或第三连接端子。因此，具有第二中心频率的射频信号通过天线或扩展天线发送到周围空间，其中第二中心频率和第一中心频率均处于特定频带。

3. 发明授权

US09136246B2 Integrated chip package structure using silicon substrate and method of manufacturing the same 有权
公开(公告)号：US09136246B2
公开(公告)日：2015-09-15
申请号：US10755042
申请日：2004-01-09
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
IPC分类号： H01L23/12 , H01L23/00 , H01L23/36 , H01L23/498 , H01L23/538 , H01L23/64
CPC分类号： H01L24/97 , H01L23/36 , H01L23/49816 , H01L23/49822 , H01L23/5389 , H01L23/642 , H01L23/645 , H01L24/19 , H01L2221/68363 , H01L2221/68377 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/351 , H01L2224/82 , H01L2924/00
摘要： An integrated chip package structure and method of manufacturing the same is by adhering dies on a silicon substrate and forming a thin-film circuit layer on top of the dies and the silicon substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

4. 发明授权

US08748227B2 Method of fabricating chip package 有权
标题翻译：制造芯片封装的方法
公开(公告)号：US08748227B2
公开(公告)日：2014-06-10
申请号：US12206754
申请日：2008-09-09
申请人： Jin-Yuan Lee , Ching-Cheng Huang , Mou-Shiung Lin
发明人： Jin-Yuan Lee , Ching-Cheng Huang , Mou-Shiung Lin
IPC分类号： H01L21/44 , H01L21/48
CPC分类号： H01L23/293 , H01L23/3114 , H01L23/49827 , H01L24/10 , H01L24/13 , H01L24/48 , H01L24/81 , H01L2224/05124 , H01L2224/05155 , H01L2224/05599 , H01L2224/05647 , H01L2224/13 , H01L2224/13099 , H01L2224/13111 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/81801 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.
摘要翻译：公开了一种芯片级封装（CSP）及其形成方法。首先将不具有常规球形安装件的单个芯片附接到具有与单个芯片上的输入/输出（I / O）焊盘相对应的开口的粘合剂基底（布线基板）复合材料，以形成复合芯片封装。然后在开口上执行球安装，从而将芯片位置处的I / O焊盘直接连接到下一级封装。在另一个实施例中，首先在晶片侧形成粘合剂层以形成等离子体，然后在CSP中将其锯切。然后将已经在其上的粘合剂的CSP粘合到基底上。复合芯片封装可以可选地用模制材料封装。 CSP提供集成和更短的芯片连接，特别适用于高频电路应用，并可以利用当前现有的测试基础架构。

5. 发明授权

US08535976B2 Method for fabricating chip package with die and substrate 有权
标题翻译：用芯片和基板制造芯片封装的方法
公开(公告)号：US08535976B2
公开(公告)日：2013-09-17
申请号：US10454972
申请日：2003-06-04
申请人： Jin-Yuan Lee , Mou-Shiung Lin , Ching-Cheng Huang
发明人： Jin-Yuan Lee , Mou-Shiung Lin , Ching-Cheng Huang
IPC分类号： H01L21/44
CPC分类号： H01L24/82 , H01L21/568 , H01L23/49822 , H01L23/49894 , H01L23/5389 , H01L24/19 , H01L24/97 , H01L2221/68377 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/13022 , H01L2224/20 , H01L2224/211 , H01L2224/24137 , H01L2224/73267 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15174 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2224/82 , H01L2924/00
摘要： An integrated chip package structure and method of manufacturing the same is by adhering dies on a ceramic substrate and forming a thin-film circuit layer on top of the dies and the ceramic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.
摘要翻译：集成芯片封装结构及其制造方法是通过将模具附着在陶瓷基板上并在模具和陶瓷基板的顶部上形成薄膜电路层。其中薄膜电路层具有电连接到模具的金属焊盘的外部电路，其延伸到模具的有效表面外部的区域，以扇出模具的金属焊盘。此外，多个有源器件和内部电路位于管芯的有效表面上。有源器件的信号通过内部电路传输到外部电路，并通过内部电路从外部电路传输回其他有源器件。此外，芯片封装结构允许将具有不同功能的多个裸片封装在集成封装中并通过外部电路电连接裸片。

6. 发明授权

US08368204B2 Chip structure and process for forming the same 有权
标题翻译：芯片结构及其形成方法
公开(公告)号：US08368204B2
公开(公告)日：2013-02-05
申请号：US13277142
申请日：2011-10-19
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
IPC分类号： H01L23/12 , H01L23/053 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76838 , H01L21/768 , H01L21/76807 , H01L23/5286 , H01L23/5329 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A chip with a metallization structure and an insulating layer with first and second openings over first and second contact points of the metallization structure, a first circuit layer connecting the first and second contact points and comprising a first trace portion, first and second via portions between the first trace portion and the first and second contact points, the first circuit layer comprising a copper layer and a first conductive layer under the copper layer and at a sidewall of the first trace portion, and a second circuit layer comprising a second trace portion with a third via portion at a bottom thereof, wherein the second circuit layer comprises another copper layer and a second conductive layer under the other copper layer and at a sidewall of the second trace portion, and a second dielectric layer comprising a portion between the first and second circuit layers.
摘要翻译：具有金属化结构的芯片和具有在金属化结构的第一和第二接触点上的第一和第二开口的绝缘层，连接第一和第二接触点的第一电路层，包括第一迹线部分，第一和第二通孔部分，所述第一迹线部分和所述第一和第二接触点，所述第一电路层包括铜层和在所述铜层下面和所述第一迹线部分的侧壁处的第一导电层，以及第二电路层，其第二通路部分在其底部，其中所述第二电路层包括另一铜层和位于所述另一铜层下方的第二导电层和所述第二迹线部分的侧壁处的第二导电层，以及第二电介质层，第二电路层。

7. 发明授权

US07915734B2 Chip structure and process for forming the same 有权
公开(公告)号：US07915734B2
公开(公告)日：2011-03-29
申请号：US12032706
申请日：2008-02-18
申请人： Jin-Yuan Lee , Mou-Shiung Lin , Ching-Cheng Huang
发明人： Jin-Yuan Lee , Mou-Shiung Lin , Ching-Cheng Huang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L24/02 , H01L24/10 , H01L24/11 , H01L24/13 , H01L27/0248 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/0401 , H01L2224/05073 , H01L2224/0558 , H01L2224/05644 , H01L2224/05655 , H01L2224/05657 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04953 , H01L2924/12044 , H01L2924/19041 , H01L2924/30105 , H01L2924/00
摘要： A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

8. 发明授权

US07470988B2 Chip structure and process for forming the same 有权
标题翻译：芯片结构及其形成方法
公开(公告)号：US07470988B2
公开(公告)日：2008-12-30
申请号：US10997145
申请日：2004-11-24
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L28/10 , H01L21/768 , H01L21/76807 , H01L21/76838 , H01L23/522 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/60 , H01L24/02 , H01L24/10 , H01L24/11 , H01L24/13 , H01L27/0251 , H01L27/0676 , H01L27/08 , H01L28/20 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/0401 , H01L2224/13 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04953 , H01L2924/12044 , H01L2924/14 , H01L2924/15174 , H01L2924/19041 , H01L2924/30105 , Y10T29/49124 , Y10T29/49204 , H01L2924/00
摘要： A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.
摘要翻译：芯片结构包括基板，第一堆叠层，钝化层和第二堆积层。基板包括放置在基板的表面上的许多电气装置。第一组合层位于基底上。第一组合层设置有第一电介质体和第一互连方案，其中第一互连方案与第一介电体内部交错并电连接到电气装置。第一互连方案由第一金属层和插塞构成，其中相邻的第一金属层通过插塞电连接。钝化层设置在第一堆叠层上并且设有暴露第一互连方案的开口。第二堆叠层形成在钝化层上。第二组合层设置有第二电介质体和第二互连方案，其中第二互连方案在第二介电体内部交织并与第一互连方案电连接。第二互连方案由至少一个第二金属层和至少一个通孔金属填料构成，其中第二金属层电连接到通孔金属填料。第二金属层的迹线的厚度，宽度和横截面积分别大于第一金属层的厚度，宽度和横截面面积。

9. 发明申请

US20080142978A1 Chip structure and process for forming the same 有权
公开(公告)号：US20080142978A1
公开(公告)日：2008-06-19
申请号：US12024998
申请日：2008-02-02
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
IPC分类号： H01L23/52
CPC分类号： H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L24/02 , H01L24/10 , H01L24/11 , H01L24/13 , H01L27/0248 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/0401 , H01L2224/05073 , H01L2224/0558 , H01L2224/05644 , H01L2224/05655 , H01L2224/05657 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04953 , H01L2924/12044 , H01L2924/19041 , H01L2924/30105 , H01L2924/00
摘要： A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

10. 发明申请

US20080113503A1 LOW FABRICATION COST, HIGH PERFORMANCE, HIGH RELIABILITY CHIP SCALE PACKAGE 有权
公开(公告)号：US20080113503A1
公开(公告)日：2008-05-15
申请号：US11930220
申请日：2007-10-31
申请人： Jin Yuan Lee , Ming Ta Lei , Ching-Cheng Huang , Chuen-Jye Lin
发明人： Jin Yuan Lee , Ming Ta Lei , Ching-Cheng Huang , Chuen-Jye Lin
IPC分类号： H01L21/441
CPC分类号： H04B1/7113 , H01L21/563 , H01L23/3114 , H01L23/3128 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/14 , H01L24/15 , H01L24/16 , H01L24/17 , H01L2224/0231 , H01L2224/0401 , H01L2224/1147 , H01L2224/11831 , H01L2224/11901 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01042 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01084 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/14 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/351 , H04B1/712 , H01L2224/13099 , H01L2924/00
摘要： The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

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