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    • 1. 发明授权
    • Method to form self-aligned source/drain CMOS device on insulated staircase oxide
    • 在绝缘阶梯氧化物上形成自对准源极/漏极CMOS器件的方法
    • US06541327B1
    • 2003-04-01
    • US09760123
    • 2001-01-16
    • Lap ChanElgin QuekRavi SundaresanYang PanJames Yong Meng LeeYing Keung LeungYelehanka Ramachandramurthy PradeepJia Zhen Zheng
    • Lap ChanElgin QuekRavi SundaresanYang PanJames Yong Meng LeeYing Keung LeungYelehanka Ramachandramurthy PradeepJia Zhen Zheng
    • H01L218238
    • H01L29/66492H01L21/823814H01L29/41783H01L29/665H01L29/66575
    • A method to form elevated source/drain (S/D) over staircase shaped openings in insulating layers. A gate structure is formed over a substrate. The gate structure is preferably comprised of a gate dielectric layer, gate electrode, first spacers, and hard mask. A first insulating layer is formed over the substrate and the gate structure. A resist layer is formed having an opening over the gate structure and over a lateral area adjacent to the gate structure. We etch the insulating layer through the opening in the resist layer. The etching removes a first thickness of the insulating layer to form a source/drain (S/D) opening. We remove the first spacers and hardmask to form a source/drain (S/D) contact opening. We implant ions into the substrate through the source/drain (S/D) contact opening to form lightly doped drain regions. We form second spacers on the sidewalls of the gate electrode and the gate dielectric and on the sidewalls of the insulating layer in the source/drain (S/D) contact opening and the source/drain (S/D) opening. A conductive layer is deposited over the gate electrode, the insulating layer. The conductive layer is planarized to exposed the insulating layer to form elevated source/drain (S/D) blocks on a staircase shape insulating layer.
    • 一种在绝缘层中的阶梯形开口形成升高的源极/漏极(S / D)的方法。 栅极结构形成在衬底上。 栅极结构优选由栅极电介质层,栅电极,第一间隔物和硬掩模组成。 在衬底和栅极结构之上形成第一绝缘层。 形成抗蚀剂层,其具有在栅极结构上方的开口以及与栅极结构相邻的横向区域。 我们通过抗蚀剂层中的开口蚀刻绝缘层。 蚀刻去除绝缘层的第一厚度以形成源极/漏极(S / D)开口。 我们移除第一个垫片和硬掩模以形成一个源极/漏极(S / D)接触开口。 我们通过源极/漏极(S / D)接触开口将离子注入到衬底中,以形成轻掺杂的漏极区。 我们在源极/漏极(S / D)接触开口和源极/漏极(S / D)开口中的栅电极和栅极电介质的侧壁和绝缘层的侧壁上形成第二间隔物。 在栅电极,绝缘层上沉积导电层。 导电层被平坦化以暴露绝缘层,以在阶梯形绝缘层上形成升高的源极/漏极(S / D)块。
    • 2. 发明授权
    • Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation
    • 通过使用选择性外延和使用注入的源极/漏极首先形成沟道来控制垂直晶体管的沟道长度的方法
    • US06436770B1
    • 2002-08-20
    • US09721720
    • 2000-11-27
    • Ying Keung LeungYelehanka Ramachandramurthy PradeepJia Zhen ZhengLap ChanElgin QuekRavi SundaresanYang PanJames Yong Meng Lee
    • Ying Keung LeungYelehanka Ramachandramurthy PradeepJia Zhen ZhengLap ChanElgin QuekRavi SundaresanYang PanJames Yong Meng Lee
    • H01L21332
    • H01L29/7827H01L29/42356H01L29/66666
    • A method for a vertical MOS transistor whose vertical channel width can be accurately defined and controlled. Isolation regions are formed in a substrate. The isolation regions defining an active area. Then, we form a source region in the active area. A dielectric layer is formed over the active area and the isolation regions. We form a barrier layer over the dielectric layer. We form an opening in the barrier layer. A gate layer is formed in the opening. We form an insulating layer over the conductive layer and the barrier layer. We form a gate opening through the insulating layer, the gate layer and the dielectric layer to expose the source region. Gate dielectric spacers are formed over the sidewalls of the gate layer. Then, we form a conductive plug filling the gate opening. The insulating layer is removed. We form a drain region in top and side portions of the conductive plug and form doped gate regions in the gate layer. The remaining portions of the conductive plug comprise a channel region. A channel length is between the top of the source region and the drain region. We form an interlevel dielectric layer over the barrier layer, the gate layer, and the conductive plug. Contacts are formed through the interlevel dielectric layer to the doped gate regions, the drain region and the source region.
    • 一种垂直MOS晶体管的方法,其垂直沟道宽度可以被精确地限定和控制。 在衬底中形成隔离区。 隔离区限定有效区域。 然后,我们在活动区域​​中形成一个源区域。 在有源区域和隔离区域上形成介电层。 我们在电介质层上形成阻挡层。 我们在屏障层形成一个开口。 在开口中形成栅极层。 我们在导电层和阻挡层上形成绝缘层。 我们通过绝缘层,栅极层和电介质层形成栅极开口以暴露源极区域。 栅极电介质隔离物形成在栅极层的侧壁上。 然后,我们形成一个填充门开口的导电塞。 绝缘层被去除。 我们在导电插塞的顶部和侧部形成漏极区,并在栅极层中形成掺杂的栅极区。 导电插塞的其余部分包括沟道区域。 沟道长度在源极区域的顶部和漏极区域之间。 我们在阻挡层,栅极层和导电插塞上形成层间电介质层。 通过层间介质层与掺杂栅极区,漏极区和源极区形成触点。
    • 4. 发明授权
    • Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner
    • 通过使用一次性间隔件/衬垫在栅电极的边缘下形成气隙的方法
    • US06468877B1
    • 2002-10-22
    • US09907651
    • 2001-07-19
    • Yelehanka Ramachandramurthy PradeepJia Zhen ZhengLap ChanElgin QuekRavi SundaresanYang PanJames Yong Meng LeeYing Keung Leung
    • Yelehanka Ramachandramurthy PradeepJia Zhen ZhengLap ChanElgin QuekRavi SundaresanYang PanJames Yong Meng LeeYing Keung Leung
    • H01L2176
    • H01L21/7682H01L21/764H01L21/823468H01L29/4983
    • A method of fabricating an air-gap spacer of a semiconductor device, comprising the following steps. A semiconductor substrate having at least a pair of STIs defining an active region is provided. A gate electrode is formed on the substrate within the active region. The gate electrode having an underlying gate dielectric layer. A liner oxide layer is formed over the structure, covering the sidewalls of the gate dielectric layer, the gate electrode, and over the top surface of the gate electrode. A liner nitride layer is formed over the liner oxide layer. A thick oxide layer is formed over the structure. The thick oxide, liner nitride, and liner oxide layers are planarized level with the top surface of the gate electrode, and exposing the liner oxide layer at either side of the gate electrode. The planarized thick oxide layer is removed with a portion of the liner oxide layer and a portion of the gate dielectric layer under the gate electrode to form a cross-section inverted T-shaped opening on either side of the gate electrode. A gate spacer oxide layer is formed over the structure at least as thick as the gate electrode, wherein the gate spacer oxide layer partially fills the inverted T-shaped opening from the top down and wherein air gap spacers are formed proximate the bottom of the inverted T-shaped opening. The gate spacer oxide, liner nitride, and liner oxide layers are etched to form gate spacers proximate the gate electrode. The gate spacers having an underlying etched liner nitride layer and liner oxide layer.
    • 一种制造半导体器件的气隙间隔物的方法,包括以下步骤。 提供具有至少一对限定有源区域的STI的半导体衬底。 在有源区内的基板上形成栅电极。 栅电极具有底层栅介电层。 在该结构上形成衬里氧化物层,覆盖栅极电介质层的侧壁,栅电极以及栅电极的顶表面。 在衬垫氧化物层上形成衬里氮化物层。 在结构上形成厚的氧化物层。 厚氧化物,衬里氮化物和衬里氧化物层与栅电极的顶表面平坦化,并且在栅电极的任一侧暴露衬里氧化物层。 用一部分衬垫氧化物层和栅电介质层的一部分在栅电极下方去除平坦化的厚氧化物层,以在栅电极的任一侧上形成横截面倒置的T形开口。 在该结构上形成至少与栅电极一样厚的栅极间隔氧化物层,其中栅极间隔物氧化物层从顶部向下部分地填充倒置的T形开口,并且其中气隙间隔物邻近倒置的底部形成 T形开口。 蚀刻栅间隔氧化物,衬里氮化物和衬里氧化物层以在栅电极附近形成栅极间隔。 栅极间隔物具有下面的蚀刻衬里氮化物层和衬里氧化物层。