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1. 发明申请

US20130113075A1 METAL-INSULATOR-METAL CAPACITOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：金属绝缘体 - 金属电容器结构及其制造方法
公开(公告)号：US20130113075A1
公开(公告)日：2013-05-09
申请号：US13292156
申请日：2011-11-09
申请人： Ji FENG , Duan-Quan Liao , Hai-Long Gu , Ying-Tu Chen
发明人： Ji FENG , Duan-Quan Liao , Hai-Long Gu , Ying-Tu Chen
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L28/60 , H01L21/283 , H01L21/3213 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor structure includes a first dielectric layer, a first damascene electrode layer, an insulating barrier layer, a second dielectric layer and a second damascene electrode layer. The first damascene electrode layer is formed in the first dielectric layer. The insulating barrier layer covers the first dielectric layer and the first damascene electrode layer, and is a single layer structure. The second dielectric layer is formed on the insulating barrier layer. The second damascene electrode layer is formed in the second dielectric layer and is contacted with the insulating barrier layer. The MIM capacitor structure can includes a dual damascene structure formed in the second dielectric layer and the insulating barrier layer and electrically connected to the first damascene electrode layer. A method for manufacturing the MIM capacitor structure is also provided.
摘要翻译：金属绝缘体金属（MIM）电容器结构包括第一电介质层，第一镶嵌电极层，绝缘阻挡层，第二电介质层和第二镶嵌电极层。第一镶嵌电极层形成在第一介电层中。绝缘阻挡层覆盖第一电介质层和第一镶嵌电极层，并且是单层结构。第二电介质层形成在绝缘阻挡层上。第二镶嵌电极层形成在第二电介质层中并与绝缘阻挡层接触。 MIM电容器结构可以包括形成在第二电介质层和绝缘阻挡层中并电连接到第一镶嵌电极层的双镶嵌结构。还提供了一种用于制造MIM电容器结构的方法。

2. 发明授权

US08946854B2 Metal-insulator-metal capacitor structure and method for manufacturing the same 有权
标题翻译：金属 - 绝缘体 - 金属电容器结构及其制造方法
公开(公告)号：US08946854B2
公开(公告)日：2015-02-03
申请号：US13292156
申请日：2011-11-09
申请人： Ji Feng , Duan-Quan Liao , Hai-Long Gu , Ying-Tu Chen
发明人： Ji Feng , Duan-Quan Liao , Hai-Long Gu , Ying-Tu Chen
IPC分类号： H01L29/02 , H01L23/522 , H01L49/02
CPC分类号： H01L28/60 , H01L21/283 , H01L21/3213 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor structure includes a first dielectric layer, a first damascene electrode layer, an insulating barrier layer, a second dielectric layer and a second damascene electrode layer. The first damascene electrode layer is formed in the first dielectric layer. The insulating barrier layer covers the first dielectric layer and the first damascene electrode layer, and is a single layer structure. The second dielectric layer is formed on the insulating barrier layer. The second damascene electrode layer is formed in the second dielectric layer and is contacted with the insulating barrier layer. The MIM capacitor structure can includes a dual damascene structure formed in the second dielectric layer and the insulating barrier layer and electrically connected to the first damascene electrode layer. A method for manufacturing the MIM capacitor structure is also provided.
摘要翻译：金属绝缘体金属（MIM）电容器结构包括第一电介质层，第一镶嵌电极层，绝缘阻挡层，第二电介质层和第二镶嵌电极层。第一镶嵌电极层形成在第一介电层中。绝缘阻挡层覆盖第一电介质层和第一镶嵌电极层，并且是单层结构。第二电介质层形成在绝缘阻挡层上。第二镶嵌电极层形成在第二电介质层中并与绝缘阻挡层接触。 MIM电容器结构可以包括形成在第二电介质层和绝缘阻挡层中并电连接到第一镶嵌电极层的双镶嵌结构。还提供了一种用于制造MIM电容器结构的方法。

3. 发明授权

US08658487B2 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08658487B2
公开(公告)日：2014-02-25
申请号：US13298395
申请日：2011-11-17
申请人： Duan-Quan Liao , Shih-Chieh Hsu , Yi-Kun Chen , Ching-Hwa Tey
发明人： Duan-Quan Liao , Shih-Chieh Hsu , Yi-Kun Chen , Ching-Hwa Tey
IPC分类号： H01L21/336
CPC分类号： H01L21/823842 , H01L29/66545
摘要： A method for fabricating a semiconductor device comprises steps as follows: A first dummy gate having a first high-k gate insulator layer, a first composite sacrificial layer, and a first dummy gate electrode sequentially stacked on a substrate is firstly provided. The first dummy gate electrode is subsequently removed to expose the first composite sacrificial layer. The first composite sacrificial layer is then removed. Thereafter, a first work function layer is formed on the first high-k gate insulator layer, and a first metal gate electrode is formed on the first work function layer.
摘要翻译：一种制造半导体器件的方法包括以下步骤：首先提供具有第一高k栅极绝缘体层，第一复合牺牲层和顺序堆叠在基板上的第一伪栅电极的第一伪栅极。随后去除第一伪栅电极以暴露第一复合牺牲层。然后去除第一复合牺牲层。此后，在第一高k栅极绝缘体层上形成第一功函数层，在第一功函数层上形成第一金属栅电极。

4. 发明授权

US08507338B2 Semiconductor structure and fabricating method thereof 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08507338B2
公开(公告)日：2013-08-13
申请号：US13204808
申请日：2011-08-08
申请人： Duan-Quan Liao , Yi-Kun Chen , Xiao-Zhong Zhu
发明人： Duan-Quan Liao , Yi-Kun Chen , Xiao-Zhong Zhu
IPC分类号： H01L21/8238 , H01L29/94
CPC分类号： H01L29/66545 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A fabricating method of semiconductor structure is provided. First, a substrate with a dielectric layer formed thereon is provided. The dielectric layer has a first opening and a second opening exposing a portion of the substrate. Further, a gate dielectric layer including a high-k dielectric layer and a barrier layer stacked thereon had been formed on the bottoms of the first opening and the second opening. Next, a sacrificial layer is formed on the portion of the gate dielectric layer within the second opening. Next, a first work function metal layer is formed to cover the portion of the gate dielectric layer within the first opening and the sacrificial layer. Then, the portion of the first work function metal layer and the sacrificial layer within the second opening are removed.
摘要翻译：提供了半导体结构的制造方法。首先，提供其上形成有介电层的基板。电介质层具有第一开口和露出衬底的一部分的第二开口。此外，在第一开口和第二开口的底部上形成了包括高k电介质层和层叠在其上的阻挡层的栅极电介质层。接下来，在第二开口内的栅介电层的部分上形成牺牲层。接下来，形成第一功函数金属层以覆盖第一开口和牺牲层内的栅介质层的部分。然后，去除第一功函数金属层的部分和第二开口内的牺牲层。

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