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1. 发明授权

US09698229B2 Semiconductor structure and process thereof 有权
公开(公告)号：US09698229B2
公开(公告)日：2017-07-04
申请号：US13351231
申请日：2012-01-17
申请人： Duan Quan Liao , Yikun Chen , Ching-Hwa Tey , Xiao Zhong Zhu
发明人： Duan Quan Liao , Yikun Chen , Ching-Hwa Tey , Xiao Zhong Zhu
IPC分类号： H01L29/76 , H01L29/417 , H01L29/78 , H01L29/51
CPC分类号： H01L21/823871 , H01L21/28518 , H01L21/76805 , H01L21/76895 , H01L21/823814 , H01L21/823821 , H01L23/535 , H01L27/0924 , H01L27/1104 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/41791 , H01L29/517 , H01L29/66545 , H01L29/7848 , H01L29/785
摘要： A semiconductor structure includes at least a fin-shaped structure, a gate, a source/drain region, an interdielectric layer and an epitaxial structure. At least a fin-shaped structure is located on a bottom substrate. The gate covers the fin-shaped structure. The source/drain region is located in the fin-shaped structure next to the gate. The interdielectric layer covers the gate and the fin-shaped structure, wherein the interdielectric layer has a plurality of contact holes, respectively exposing at least a part of the source/drain region. The epitaxial structure is located in each of the contact holes, directly contacts and is only located on the source/drain region. Additionally, a semiconductor process formed said semiconductor structure is also provided.

2. 发明授权

US08658487B2 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08658487B2
公开(公告)日：2014-02-25
申请号：US13298395
申请日：2011-11-17
申请人： Duan-Quan Liao , Shih-Chieh Hsu , Yi-Kun Chen , Ching-Hwa Tey
发明人： Duan-Quan Liao , Shih-Chieh Hsu , Yi-Kun Chen , Ching-Hwa Tey
IPC分类号： H01L21/336
CPC分类号： H01L21/823842 , H01L29/66545
摘要： A method for fabricating a semiconductor device comprises steps as follows: A first dummy gate having a first high-k gate insulator layer, a first composite sacrificial layer, and a first dummy gate electrode sequentially stacked on a substrate is firstly provided. The first dummy gate electrode is subsequently removed to expose the first composite sacrificial layer. The first composite sacrificial layer is then removed. Thereafter, a first work function layer is formed on the first high-k gate insulator layer, and a first metal gate electrode is formed on the first work function layer.
摘要翻译：一种制造半导体器件的方法包括以下步骤：首先提供具有第一高k栅极绝缘体层，第一复合牺牲层和顺序堆叠在基板上的第一伪栅电极的第一伪栅极。随后去除第一伪栅电极以暴露第一复合牺牲层。然后去除第一复合牺牲层。此后，在第一高k栅极绝缘体层上形成第一功函数层，在第一功函数层上形成第一金属栅电极。

3. 发明申请

US20120299099A1 FINFET TRANSISTOR STRUCTURE AND METHOD FOR MAKING THE SAME 有权
标题翻译： FINFET晶体管结构及其制造方法
公开(公告)号：US20120299099A1
公开(公告)日：2012-11-29
申请号：US13116018
申请日：2011-05-26
申请人： Rai-Min Huang , Sheng-Huei Dai , Chen-Hua Tsai , Duan Quan Liao , Yikun Chen , Xiao Zhong Zhu
发明人： Rai-Min Huang , Sheng-Huei Dai , Chen-Hua Tsai , Duan Quan Liao , Yikun Chen , Xiao Zhong Zhu
IPC分类号： H01L29/786 , H01L21/3205
CPC分类号： H01L29/0653 , H01L27/10826 , H01L27/10879 , H01L29/66795 , H01L29/785 , H01L29/7854
摘要： A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.
摘要翻译： FINFET晶体管结构包括衬底，鳍结构，绝缘层和栅极结构。翅片结构设置在基板上并直接连接到基板。此外，翅片结构包括翅片导电层和瓶颈。绝缘层覆盖基板，并且具有通过部分地围绕翅片结构的瓶颈而形成的突出侧，以及与基板直接接触的底侧，使得突出侧延伸到翅片结构的下方。门结构部分地围绕翅片结构。

4. 发明申请

US20130181264A1 SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF 有权
标题翻译：半导体结构及其工艺
公开(公告)号：US20130181264A1
公开(公告)日：2013-07-18
申请号：US13351231
申请日：2012-01-17
申请人： Duan Quan Liao , Yikun Chen , Ching-Hwa Tey , Xiao Zhong Zhu
发明人： Duan Quan Liao , Yikun Chen , Ching-Hwa Tey , Xiao Zhong Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823871 , H01L21/28518 , H01L21/76805 , H01L21/76895 , H01L21/823814 , H01L21/823821 , H01L23/535 , H01L27/0924 , H01L27/1104 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/41791 , H01L29/517 , H01L29/66545 , H01L29/7848 , H01L29/785
摘要： A semiconductor structure includes at least a fin-shaped structure, a gate, a source/drain region, an interdielectric layer and an epitaxial structure. At least a fin-shaped structure is located on a bottom substrate. The gate covers the fin-shaped structure. The source/drain region is located in the fin-shaped structure next to the gate. The interdielectric layer covers the gate and the fin-shaped structure, wherein the interdielectric layer has a plurality of contact holes, respectively exposing at least a part of the source/drain region. The epitaxial structure is located in each of the contact holes, directly contacts and is only located on the source/drain region. Additionally, a semiconductor process formed said semiconductor structure is also provided.
摘要翻译：半导体结构至少包括鳍状结构，栅极，源极/漏极区，电介质层和外延结构。至少一个鳍状结构位于底部基底上。门覆盖鳍状结构。源极/漏极区域位于栅极旁边的鳍状结构中。电介质层覆盖栅极和鳍状结构，其中介电层具有多个接触孔，分别暴露出源/漏区的至少一部分。外延结构位于每个接触孔中，直接接触并且仅位于源/漏区上。此外，还提供了形成所述半导体结构的半导体工艺。

5. 发明申请

US20130130460A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130130460A1
公开(公告)日：2013-05-23
申请号：US13298395
申请日：2011-11-17
申请人： Duan-Quan LIAO , Shih-Chieh Hsu , Yi-Kun Chen , Ching-Hwa Tey
发明人： Duan-Quan LIAO , Shih-Chieh Hsu , Yi-Kun Chen , Ching-Hwa Tey
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L21/823842 , H01L29/66545
摘要： A method for fabricating a semiconductor device comprises steps as follows: A first dummy gate having a first high-k gate insulator layer, a first composite sacrificial layer, and a first dummy gate electrode sequentially stacked on a substrate is firstly provided. The first dummy gate electrode is subsequently removed to expose the first composite sacrificial layer. The first composite sacrificial layer is then removed. Thereafter, a first work function layer is formed on the first high-k gate insulator layer, and a first metal gate electrode is formed on the first work function layer.
摘要翻译：一种制造半导体器件的方法包括以下步骤：首先提供具有第一高k栅极绝缘体层，第一复合牺牲层和顺序堆叠在基板上的第一伪栅电极的第一伪栅极。随后去除第一伪栅电极以暴露第一复合牺牲层。然后去除第一复合牺牲层。此后，在第一高k栅极绝缘体层上形成第一功函数层，在第一功函数层上形成第一金属栅电极。

6. 发明申请

US20130113075A1 METAL-INSULATOR-METAL CAPACITOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：金属绝缘体 - 金属电容器结构及其制造方法
公开(公告)号：US20130113075A1
公开(公告)日：2013-05-09
申请号：US13292156
申请日：2011-11-09
申请人： Ji FENG , Duan-Quan Liao , Hai-Long Gu , Ying-Tu Chen
发明人： Ji FENG , Duan-Quan Liao , Hai-Long Gu , Ying-Tu Chen
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L28/60 , H01L21/283 , H01L21/3213 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor structure includes a first dielectric layer, a first damascene electrode layer, an insulating barrier layer, a second dielectric layer and a second damascene electrode layer. The first damascene electrode layer is formed in the first dielectric layer. The insulating barrier layer covers the first dielectric layer and the first damascene electrode layer, and is a single layer structure. The second dielectric layer is formed on the insulating barrier layer. The second damascene electrode layer is formed in the second dielectric layer and is contacted with the insulating barrier layer. The MIM capacitor structure can includes a dual damascene structure formed in the second dielectric layer and the insulating barrier layer and electrically connected to the first damascene electrode layer. A method for manufacturing the MIM capacitor structure is also provided.
摘要翻译：金属绝缘体金属（MIM）电容器结构包括第一电介质层，第一镶嵌电极层，绝缘阻挡层，第二电介质层和第二镶嵌电极层。第一镶嵌电极层形成在第一介电层中。绝缘阻挡层覆盖第一电介质层和第一镶嵌电极层，并且是单层结构。第二电介质层形成在绝缘阻挡层上。第二镶嵌电极层形成在第二电介质层中并与绝缘阻挡层接触。 MIM电容器结构可以包括形成在第二电介质层和绝缘阻挡层中并电连接到第一镶嵌电极层的双镶嵌结构。还提供了一种用于制造MIM电容器结构的方法。

7. 发明申请

US20120309196A1 MANUFACTURING METHOD FOR DUAL DAMASCENE STRUCTURE 有权
标题翻译：双重结构结构的制造方法
公开(公告)号：US20120309196A1
公开(公告)日：2012-12-06
申请号：US13150145
申请日：2011-06-01
申请人： SHOUGANG MI , Duan Quan Liao
发明人： SHOUGANG MI , Duan Quan Liao
IPC分类号： H01L21/306
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/76811 , H01L21/76816
摘要： A manufacturing method for a dual damascene structure includes providing a substrate having a dielectric layer, a first hard mask layer and a second hard mask layer sequentially formed thereon, performing a first double patterning process to sequentially form a plurality of first trench openings and a plurality of second trench openings in the second hard mask layer, performing a second double patterning process to sequentially form a plurality of first via openings and a plurality of second via openings in the fist hard mask layer, and transferring the first trench openings, the second trench openings, the first via openings, and the second via openings to the dielectric layer to form a plurality of dual damascene openings.
摘要翻译：一种用于双镶嵌结构的制造方法包括提供具有介电层，第一硬掩模层和顺序地形成在其上的第二硬掩模层的基板，执行第一双重图案化工艺以顺序地形成多个第一沟槽开口和多个第一沟槽开口的第二硬掩模层中的第二沟槽开口，执行第二双重图案化处理以顺序地形成第一硬掩模层中的多个第一通孔开口和多个第二通孔，并且传送第一沟槽开口，第二沟槽开口，第一通孔开口和第二通孔开口到介电层，以形成多个双镶嵌开口。

8. 发明授权

US08946854B2 Metal-insulator-metal capacitor structure and method for manufacturing the same 有权
标题翻译：金属 - 绝缘体 - 金属电容器结构及其制造方法
公开(公告)号：US08946854B2
公开(公告)日：2015-02-03
申请号：US13292156
申请日：2011-11-09
申请人： Ji Feng , Duan-Quan Liao , Hai-Long Gu , Ying-Tu Chen
发明人： Ji Feng , Duan-Quan Liao , Hai-Long Gu , Ying-Tu Chen
IPC分类号： H01L29/02 , H01L23/522 , H01L49/02
CPC分类号： H01L28/60 , H01L21/283 , H01L21/3213 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor structure includes a first dielectric layer, a first damascene electrode layer, an insulating barrier layer, a second dielectric layer and a second damascene electrode layer. The first damascene electrode layer is formed in the first dielectric layer. The insulating barrier layer covers the first dielectric layer and the first damascene electrode layer, and is a single layer structure. The second dielectric layer is formed on the insulating barrier layer. The second damascene electrode layer is formed in the second dielectric layer and is contacted with the insulating barrier layer. The MIM capacitor structure can includes a dual damascene structure formed in the second dielectric layer and the insulating barrier layer and electrically connected to the first damascene electrode layer. A method for manufacturing the MIM capacitor structure is also provided.
摘要翻译：金属绝缘体金属（MIM）电容器结构包括第一电介质层，第一镶嵌电极层，绝缘阻挡层，第二电介质层和第二镶嵌电极层。第一镶嵌电极层形成在第一介电层中。绝缘阻挡层覆盖第一电介质层和第一镶嵌电极层，并且是单层结构。第二电介质层形成在绝缘阻挡层上。第二镶嵌电极层形成在第二电介质层中并与绝缘阻挡层接触。 MIM电容器结构可以包括形成在第二电介质层和绝缘阻挡层中并电连接到第一镶嵌电极层的双镶嵌结构。还提供了一种用于制造MIM电容器结构的方法。

9. 发明授权

US08828878B2 Manufacturing method for dual damascene structure 有权
标题翻译：双镶嵌结构的制造方法
公开(公告)号：US08828878B2
公开(公告)日：2014-09-09
申请号：US13218458
申请日：2011-08-26
申请人： Duan Quan Liao , Yikun Chen , Xiao Zhong Zhu , Ching-Hwa Tey , Chen-Hua Tsai , Yu-Tsung Lai
发明人： Duan Quan Liao , Yikun Chen , Xiao Zhong Zhu , Ching-Hwa Tey , Chen-Hua Tsai , Yu-Tsung Lai
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/311 , H01L21/768
CPC分类号： H01L21/31116 , H01L21/31144 , H01L21/76811 , H01L21/76816
摘要： A manufacturing method for a dual damascene structure first includes providing a substrate having at least a dielectric layer, a first hard mask layer, a first cap layer, a second hard mask layer, and a second cap layer sequentially formed thereon, performing a first double patterning process to form a plurality of first trench openings and second trench openings in the second cap layer and the second hard mask, and the first layer being exposed in bottoms of the first trench openings and the second trench openings, performing a second double patterning process to form a plurality of first via openings and second via openings in the first cap layer and the first hard mask layer, and transferring the first trench openings, the second trench openings, the first via openings, and the second via openings to the dielectric layer to form a plurality of dual damascene openings.
摘要翻译：一种用于双镶嵌结构的制造方法首先包括提供具有至少介电层，第一硬掩模层，第一盖层，第二硬掩模层和顺序地形成在其上的第二盖层的基板，执行第一双在第二盖层和第二硬掩模中形成多个第一沟槽开口和第二沟槽开口，并且第一层暴露在第一沟槽开口和第二沟槽开口的底部中，执行第二双重图案化工艺以在第一盖层和第一硬掩模层中形成多个第一通孔和第二通孔，并将第一沟槽开口，第二沟槽开口，第一通孔开口和第二通孔开口传递到介电层以形成多个双镶嵌开口。

10. 发明申请

US20130037889A1 SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130037889A1
公开(公告)日：2013-02-14
申请号：US13204808
申请日：2011-08-08
申请人： Duan-Quan LIAO , Yi-Kun Chen , Xiao-Zhong Zhu
发明人： Duan-Quan LIAO , Yi-Kun Chen , Xiao-Zhong Zhu
IPC分类号： H01L29/78 , H01L21/8234
CPC分类号： H01L29/66545 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A fabricating method of semiconductor structure is provided. First, a substrate with a dielectric layer formed thereon is provided. The dielectric layer has a first opening and a second opening exposing a portion of the substrate. Further, a gate dielectric layer including a high-k dielectric layer and a barrier layer stacked thereon had been formed on the bottoms of the first opening and the second opening. Next, a sacrificial layer is formed on the portion of the gate dielectric layer within the second opening. Next, a first work function metal layer is formed to cover the portion of the gate dielectric layer within the first opening and the sacrificial layer. Then, the portion of the first work function metal layer and the sacrificial layer within the second opening are removed.
摘要翻译：提供了半导体结构的制造方法。首先，提供其上形成有介电层的基板。电介质层具有第一开口和露出衬底的一部分的第二开口。此外，在第一开口和第二开口的底部上形成了包括高k电介质层和层叠在其上的阻挡层的栅极电介质层。接下来，在第二开口内的栅介电层的部分上形成牺牲层。接下来，形成第一功函数金属层以覆盖第一开口和牺牲层内的栅介质层的部分。然后，去除第一功函数金属层的部分和第二开口内的牺牲层。

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