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1. 发明授权

US08451292B2 Video summarization method based on mining story structure and semantic relations among concept entities thereof 有权
标题翻译：基于概念实体之间的挖掘故事结构和语义关系的视频摘要方法
公开(公告)号：US08451292B2
公开(公告)日：2013-05-28
申请号：US12623466
申请日：2009-11-23
申请人： Jhing-Fa Wang , Bo-Wei Chen , Jia-Ching Wang , Chia-Hung Chang
发明人： Jhing-Fa Wang , Bo-Wei Chen , Jia-Ching Wang , Chia-Hung Chang
IPC分类号： G09G5/00 , G06T11/20
CPC分类号： G06T11/206 , G06F17/30843 , G11B27/034 , G11B27/28 , G11B27/322
摘要： A video summarized method based on mining the story structure and semantic relations among concept entities has steps of processing a video to generate multiple important shots that are annotated with respective keywords: Performing a concept expansion process by using the keywords to create expansion trees for the annotated shots; rearranging the keywords of the expansion trees and classifying to calculate relations thereof; applying a graph entropy algorithm to determine significant shots and edges interconnected with the shots. Based on the determined result of the graph entropy algorithm, a structured relational graph is built to display the significant shots and edges thereof. Consequently, users can more rapidly browse the content of a video and comprehend if different shots are related.
摘要翻译：基于挖掘概念实体之间的故事结构和语义关系的视频汇总方法具有处理视频以生成多个重要照片的步骤，这些重要照片用相应的关键字注释：通过使用关键字创建扩展树来创建注释的概念扩展过程射击重新布置扩展树的关键字并进行分类以计算其关系; 应用图熵算法来确定与镜头相互连接的重要镜头和边缘。基于图熵算法的确定结果，建立了结构化关系图，以显示其重要的镜头和边缘。因此，用户可以更快速地浏览视频的内容，并理解如果不同的镜头相关。

2. 发明申请

US20120119790A1 DYNAMIC COMPARATOR BASED COMPARISON SYSTEM 有权
标题翻译：基于动态比较器的比较系统
公开(公告)号：US20120119790A1
公开(公告)日：2012-05-17
申请号：US12981516
申请日：2010-12-30
申请人： Bo-Wei Chen
发明人： Bo-Wei Chen
IPC分类号： H03K5/22
CPC分类号： H03K3/356139
摘要： A comparison system including a dynamic comparator, a background offset calibration circuit, and an asynchronous reset timing control circuit is presented. The background offset calibration circuit is coupled to the dynamic comparator, and generates calibration signals in response to reference switching control signals. Where calibration signals are used to calibrate the input refer offset of the dynamic comparator. The asynchronous reset timing control circuit is coupled to the dynamic comparator and the background offset calibration circuit, and generates a control clock signal and the reference switching control signals in response to the output signals of the dynamic comparator and a plurality of basic clock signals. During each clock cycle of the first basic clock signal, the control clock signal is used to control the dynamic comparator to perform two data comparison, one for the input refer offset and the other for a differential input signal.
摘要翻译：提出了包括动态比较器，背景偏移校准电路和异步复位定时控制电路的比较系统。背景偏移校准电路耦合到动态比较器，并响应于参考开关控制信号产生校准信号。校准信号用于校准动态比较器的输入参考偏移量。异步复位定时控制电路耦合到动态比较器和背景偏移校准电路，并且响应于动态比较器的输出信号和多个基本时钟信号产生控制时钟信号和参考开关控制信号。在第一基本时钟信号的每个时钟周期期间，控制时钟信号用于控制动态比较器执行两个数据比较，一个用于输入参考偏移，另一个用于差分输入信号。

3. 发明授权

US08111405B2 Automatic scan and mark apparatus 有权
标题翻译：自动扫描和标记装置
公开(公告)号：US08111405B2
公开(公告)日：2012-02-07
申请号：US12547867
申请日：2009-08-26
申请人： Wen-Yuh Jywe , Chien-Hung Liu , Hung-Shu Wang , Bo-Wei Chen , Jyun-Jia Yang , Wei-Cheng Tsai , Wei-Chung Chang , Ming-Chi Chiang , Jia-Hong Chen
发明人： Wen-Yuh Jywe , Chien-Hung Liu , Hung-Shu Wang , Bo-Wei Chen , Jyun-Jia Yang , Wei-Cheng Tsai , Wei-Chung Chang , Ming-Chi Chiang , Jia-Hong Chen
IPC分类号： G01B11/30 , G01B11/14
CPC分类号： G01B11/30 , B41J3/4073 , G01B11/026
摘要： An automatic scan and mark apparatus has a machine tool, a location detection module, a laser detector, an ink jet and a control computer. The machine tool has a movable module and a stage. The stage mounts and holds a specimen having a scraped surface. The control computer controls the location detection module to determine a position of the movable module, controls the laser detector to detect a surface morphology of the scraped surface in a measurement range, and activates the ink jet to eject inks on high points of the scraped surface of the specimen. Thus, the surface morphology is built automatically and high points are screened out and marked by colored ink. Manufacturer may easily redo scraping of determined high points based on the marked location on the specimen without burdensome measurement.
摘要翻译：自动扫描和标记装置具有机床，位置检测模块，激光检测器，喷墨和控制计算机。机床具有可移动模块和平台。舞台安装并保持具有刮表面的样本。控制计算机控制位置检测模块以确定可移动模块的位置，控制激光检测器以在测量范围内检测刮削表面的表面形态，并激活喷墨以在刮削表面的高点上喷射油墨的样本。因此，自动构建表面形态，并筛选出高分，并用彩色墨水标记。制造商可以根据样品上的标记位置轻松地重新划定确定的高点，而不用繁重的测量。

4. 发明申请

US20080143576A1 ANALOG-TO-DIGITAL CONVERTING SYSTEM 有权
标题翻译：模拟数字转换系统
公开(公告)号：US20080143576A1
公开(公告)日：2008-06-19
申请号：US11941981
申请日：2007-11-19
申请人： Bo-Wei Chen , Szu-Kang Hsien
发明人： Bo-Wei Chen , Szu-Kang Hsien
IPC分类号： H03M1/34
CPC分类号： H03M1/145 , H03M1/365 , H03M1/46
摘要： A novel analog-to-digital converter (ADC) architecture using subranging successive approximation approach is disclosed. The ADC architecture is capable of achieving high sampling rate, low power consumption and low complexity. It is also able to advance the chip production yield and area utilization ratio. The new proposed ADC is formed by combining a flash converter having high sampling rate and low resolution with a successive approximation converter having low power consumption and low sampling rate.
摘要翻译：公开了一种使用次级逐次逼近方法的新型模数转换器（ADC）架构。 ADC架构能够实现高采样率，低功耗和低复杂度。也可以提高芯片产量和面积利用率。新提出的ADC通过将具有高采样率和低分辨率的闪速转换器与具有低功耗和低采样率的逐次逼近转换器组合而形成。

5. 发明授权

US08198921B2 Dynamic comparator with background offset calibration 有权
标题翻译：具有背景偏移校准的动态比较器
公开(公告)号：US08198921B2
公开(公告)日：2012-06-12
申请号：US12640016
申请日：2009-12-17
申请人： Bo-Wei Chen , Tim-Kuei Shia , Ji-Eun Jang
发明人： Bo-Wei Chen , Tim-Kuei Shia , Ji-Eun Jang
IPC分类号： H03K5/22
CPC分类号： H03K5/2481
摘要： A dynamic comparator with background offset calibration is provided. The dynamic comparator includes at least one input differential pair, a first back-to-back inverter, a second back-to-back inverter, and an integrator. The input differential pair includes two current branches, wherein one of the current branches has an input referred offset. The first back-to-back inverter determines which one of the two current branches has the input referred offset in response to a first clock signal and generates two control signals accordingly. The integrator generates two calibration voltages for the input differential pair in response to the two control signals, so as to calibrate the input referred offset. The second back-to-back inverter determines a difference between two input signals received by the input differential pair after the input referred offset is calibrated in response to a second clock signal and outputs two comparison signals accordingly.
摘要翻译：提供了具有背景偏移校准的动态比较器。动态比较器包括至少一个输入差分对，第一背对背反相器，第二背对背反相器和积分器。输入差分对包括两个电流分支，其中当前分支中的一个具有输入参考偏移。第一背对背反相器确定两个电流分支中的哪一个响应于第一时钟信号而具有参考的输入偏移，并相应地产生两个控制信号。积分器响应于两个控制信号为输入差分对产生两个校准电压，以校准输入参考偏移。第二背对背逆变器确定在响应于第二时钟信号校准输入参考偏移之后由输入差分对接收的两个输入信号之间的差异，并相应地输出两个比较信号。

6. 发明申请

US20110267145A1 COMPARISON APPARATUS AND SPEED-UP METHOD FOR COMPARATOR 审中-公开
标题翻译：比较器的比较装置和速度比较方法
公开(公告)号：US20110267145A1
公开(公告)日：2011-11-03
申请号：US12832970
申请日：2010-07-08
申请人： Ming-Hau Tseng , Yung-Pin Lee , Bo-Wei Chen
发明人： Ming-Hau Tseng , Yung-Pin Lee , Bo-Wei Chen
IPC分类号： H03F3/45
CPC分类号： H03F3/45188 , H03F1/0266 , H03F2200/78 , H03F2203/45641 , H03F2203/45644
摘要： A comparison apparatus and a speed-up method for comparator are provided. The comparison apparatus consists of a comparator and a bias modulator. The bias modulator receives input signals of the comparator to provide a set of output signals modulated according to the input signals. The set of output signals dynamically adjust body voltages of transistors in a positive feedback network of the comparator to increase a switching speed of the transistors. Therefore, an operation speed of the comparator can also be increased.
摘要翻译：提供了一种用于比较器的比较装置和加速方法。比较装置由比较器和偏置调制器组成。偏置调制器接收比较器的输入信号，以提供根据输入信号调制的一组输出信号。该组输出信号在比较器的正反馈网络中动态地调节晶体管的体电压，以增加晶体管的切换速度。因此，也可以提高比较器的动作速度。

7. 发明授权

US07515083B2 Analog-to-digital converting system 有权
标题翻译：模数转换系统
公开(公告)号：US07515083B2
公开(公告)日：2009-04-07
申请号：US11941981
申请日：2007-11-19
申请人： Bo-Wei Chen , Szu-Kang Hsien
发明人： Bo-Wei Chen , Szu-Kang Hsien
IPC分类号： H03M1/14 , H03M1/36 , H03M1/46
CPC分类号： H03M1/145 , H03M1/365 , H03M1/46
摘要： A novel analog-to-digital converter (ADC) architecture using subranging successive approximation approach is disclosed. The ADC architecture is capable of achieving high sampling rate, low power consumption and low complexity. It is also able to advance the chip production yield and area utilization ratio. The new proposed ADC is formed by combining a flash converter having high sampling rate and low resolution with a successive approximation converter having low power consumption and low sampling rate.
摘要翻译：公开了一种使用次级逐次逼近方法的新型模数转换器（ADC）架构。 ADC架构能够实现高采样率，低功耗和低复杂度。也可以提高芯片产量和面积利用率。新提出的ADC通过将具有高采样率和低分辨率的闪速转换器与具有低功耗和低采样率的逐次逼近转换器组合而形成。

8. 发明授权

US07435618B2 Method to manufacture a coreless packaging substrate 有权
标题翻译：制造无芯封装基板的方法
公开(公告)号：US07435618B2
公开(公告)日：2008-10-14
申请号：US11635034
申请日：2006-12-07
申请人： Bo-Wei Chen , Hsien-Shou Wang , Shih-Ping Hsu
发明人： Bo-Wei Chen , Hsien-Shou Wang , Shih-Ping Hsu
IPC分类号： H01L21/00 , H01L21/44 , H01L21/4763
CPC分类号： H05K3/4007 , H01L21/4857 , H01L21/6835 , H01L23/49822 , H01L2924/0002 , H05K1/113 , H05K3/0035 , H05K3/007 , H05K3/108 , H05K3/243 , H05K3/28 , H05K3/4682 , H05K2201/09436 , H05K2201/09563 , H05K2201/096 , H05K2203/0152 , H05K2203/0376 , H01L2924/00
摘要： A method for manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless packaging substrate with high density of circuit layout, less manufacturing steps, and small size.
摘要翻译：公开了一种无芯封装基板的制造方法。该方法可以制造无芯封装衬底，其包括：至少具有第一焊料掩模和第二焊料掩模的堆积结构，其中在第一和第二焊料掩模中形成多个开口以暴露出建筑结构; 以及形成在导电焊盘上的多个焊料凸块以及焊料层。因此，本发明可以生产具有高密度电路布局，较少制造步骤和小尺寸的无芯封装衬底。

9. 发明申请

US20130162456A1 ANALOG TO DIGITAL CONVERTING APPARATUS AND METHOD THEREOF 有权
标题翻译：模拟数字转换设备及其方法
公开(公告)号：US20130162456A1
公开(公告)日：2013-06-27
申请号：US13410303
申请日：2012-03-02
申请人： Bo-Wei Chen
发明人： Bo-Wei Chen
IPC分类号： H03M1/12
CPC分类号： H03M1/42
摘要： An analog-to-digital converting (ADC) apparatus is disclosed. The ADC apparatus includes a coarse comparing module, at least one pre-switching detection module, at least one fine comparing module, and an encoder. The coarse comparing module compares an input signal and a plurality of first reference signals to generate a previous comparing result and a coarse comparing result in sequence. The pre-switching detection module generates a plurality of previous selecting signals according to the received previous comparing result. The encoder generates a previous encoding result according to the coarse comparing result. The fine comparing module selects a selected reference signal to be compared with the input signal from a plurality of second reference signals according to the previous selecting signals and the previous encoding result, so as to generate a fine comparing result.
摘要翻译：公开了一种模拟 - 数字转换（ADC）装置。 ADC装置包括粗略比较模块，至少一个预切换检测模块，至少一个精细比较模块和编码器。粗略比较模块比较输入信号和多个第一参考信号以产生先前的比较结果和粗略的比较结果。预切换检测模块根据接收到的先前比较结果生成多个先前的选择信号。编码器根据粗略比较结果生成先前的编码结果。精细比较模块根据先前的选择信号和先前的编码结果选择要与多个第二参考信号的输入信号进行比较的所选择的参考信号，以产生精细的比较结果。

10. 发明授权

US08334717B2 Dynamic comparator based comparison system 有权
标题翻译：基于动态比较器的比较系统
公开(公告)号：US08334717B2
公开(公告)日：2012-12-18
申请号：US12981516
申请日：2010-12-30
申请人： Bo-Wei Chen
发明人： Bo-Wei Chen
IPC分类号： H03L5/00
CPC分类号： H03K3/356139
摘要： A comparison system including a dynamic comparator, a background offset calibration circuit, and an asynchronous reset timing control circuit is presented. The background offset calibration circuit is coupled to the dynamic comparator, and generates calibration signals in response to reference switching control signals. Where calibration signals are used to calibrate the input refer offset of the dynamic comparator. The asynchronous reset timing control circuit is coupled to the dynamic comparator and the background offset calibration circuit, and generates a control clock signal and the reference switching control signals in response to the output signals of the dynamic comparator and a plurality of basic clock signals. During each clock cycle of the first basic clock signal, the control clock signal is used to control the dynamic comparator to perform two data comparison, one for the input refer offset and the other for a differential input signal.
摘要翻译：提出了包括动态比较器，背景偏移校准电路和异步复位定时控制电路的比较系统。背景偏移校准电路耦合到动态比较器，并响应于参考开关控制信号产生校准信号。校准信号用于校准动态比较器的输入参考偏移量。异步复位定时控制电路耦合到动态比较器和背景偏移校准电路，并且响应于动态比较器的输出信号和多个基本时钟信号产生控制时钟信号和参考开关控制信号。在第一基本时钟信号的每个时钟周期期间，控制时钟信号用于控制动态比较器执行两个数据比较，一个用于输入参考偏移，另一个用于差分输入信号。

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