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1. 发明授权

US08776050B2 Distributed virtual machine monitor for managing multiple virtual resources across multiple physical nodes 有权
标题翻译：分布式虚拟机监视器，用于跨多个物理节点管理多个虚拟资源
公开(公告)号：US08776050B2
公开(公告)日：2014-07-08
申请号：US10972762
申请日：2004-10-25
申请人： Jerry Plouffe , Scott H. Davis , Alexander D. Vasilevsky , Benjamin J. Thomas, III , Steven S. Noyes , Tom Hazel
发明人： Jerry Plouffe , Scott H. Davis , Alexander D. Vasilevsky , Benjamin J. Thomas, III , Steven S. Noyes , Tom Hazel
IPC分类号： G06F9/455 , G06F9/46 , G06F9/50
CPC分类号： G06F9/5077 , G06F9/455 , G06F9/45533 , G06F9/45537 , G06F9/45558 , G06F9/4856 , G06F9/50 , G06F9/505 , G06F9/5083
摘要： A management capability is provided for a virtual computing platform. In one example, this platform allows interconnected physical resources such as processors, memory, network interfaces and storage interfaces to be abstracted and mapped to virtual resources (e.g., virtual mainframes, virtual partitions). Virtual resources contained in a virtual partition can be assembled into virtual servers that execute a guest operating system (e.g., Linux). In one example, the abstraction is unique in that any resource is available to any virtual server regardless of the physical boundaries that separate the resources. For example, any number of physical processors or any amount of physical memory can be used by a virtual server even if these resources span different nodes.
摘要翻译：为虚拟计算平台提供管理功能。在一个示例中，该平台允许诸如处理器，存储器，网络接口和存储接口之类的互连物理资源被抽象并映射到虚拟资源（例如，虚拟主机，虚拟分区）。包含在虚拟分区中的虚拟资源可以组合成执行客户操作系统（例如，Linux）的虚拟服务器。在一个示例中，抽象是唯一的，因为任何资源都可用于任何虚拟服务器，而不管分离资源的物理边界。例如，即使这些资源跨越不同的节点，虚拟服务器也可以使用任何数量的物理处理器或任何数量的物理内存。

2. 发明授权

US07529263B1 Local area-networked system having intelligent traffic control and efficient bandwidth management 有权
标题翻译：具有智能流量控制和高效带宽管理的局域网系统
公开(公告)号：US07529263B1
公开(公告)日：2009-05-05
申请号：US10345870
申请日：2003-01-16
申请人： Carlton J. Sparrell , Alexander D. Vasilevsky , Chester Ruszczyk , Jinyou Zhang
发明人： Carlton J. Sparrell , Alexander D. Vasilevsky , Chester Ruszczyk , Jinyou Zhang
IPC分类号： H04L12/64
CPC分类号： H04L12/2838 , H04L12/2834 , H04L47/10 , H04L47/13 , H04L47/2475 , H04L2012/2849 , Y02D70/10
摘要： A centralized interactive TV recording and reproduction system linking several “Quality of Service” (QoS) reproduction and control units (such as television and audio reproduction receivers), as well as high bandwidth non-QoS legacy devices such as PCs, via a Home Area Network (HAN) to a centralized media server, has novel traffic control to prevent non-QoS devices from establishing and maintaining high-bandwidth network connections during the real-time transmission of media (video and/or audio) information from the media server to the QoS devices. In the preferred embodiment, the media server also contains a gateway device for connecting the HAN to a Wide Area Network, Metropolitan Area Network, and/or the Internet, and the media server also receives video and audio signals from sources such as cable, satellite, terrestrial broadcast, etc. The media server also contains a network router. All traffic from non-QoS devices is routed through the media server, and the media server limits the delivery of packets sent from source non-QoS devices to destination non-QoS devices. As a further refinement to prevent interruptions in real-time transmissions of video and audio information to QoS devices, the information can be buffered at the QoS device level.
摘要翻译：一个集中的交互式电视记录和再现系统，通过家庭区域连接多个“服务质量”（QoS）再现和控制单元（如电视和音频再现接收机）以及高带宽非QoS传统设备（如PC）网络（HAN）到集中式媒体服务器，具有新颖的流量控制，以防止非QoS设备在从媒体服务器到媒体（视频和/或音频）信息的实时传输期间建立和维护高带宽网络连接 QoS设备。在优选实施例中，媒体服务器还包括用于将HAN连接到广域网，城域网和/或因特网的网关设备，并且媒体服务器还从源（例如有线，卫星）接收视频和音频信号，地面广播等。媒体服务器还包含一个网络路由器。来自非QoS设备的所有业务通过媒体服务器路由，媒体服务器限制从源非QoS设备发送到目的非QoS设备的数据包传送。作为进一步改进以防止将视频和音频信息实时传输到QoS设备的中断，可以在QoS设备级别缓冲信息。

3. 发明授权

US5551039A Compiling a source code vector instruction by generating a subgrid loop for iteratively processing array elements by plural processing elements 失效
标题翻译：通过生成用于通过多个处理元素反复处理数组元素的子网格循环来编译源代码向量指令
公开(公告)号：US5551039A
公开(公告)日：1996-08-27
申请号：US315662
申请日：1994-09-30
申请人： Tobias M. Weinberg , Lisa A. Tennies , Alexander D. Vasilevsky
发明人： Tobias M. Weinberg , Lisa A. Tennies , Alexander D. Vasilevsky
IPC分类号： G06F9/45
CPC分类号： G06F8/445 , G06F9/30036
摘要： A software compiler having a code generator and a scheduler. The code generator transforms a lowered intermediate representation (IR) of a source computer program, written in a known computer language, to an assembly language program written in a non-standard instruction set. In particular, the code generator translates vector instructions in the lowered IR to vector instructions from the non-standard instruction set. The vector instructions from the non-standard instruction set are defined such that assembly language programs written with them do not suffer from the effects of pipeline delays. Therefore, according to the present invention, the code generator eliminates the effects of pipeline delays when transforming the lowered IR to the assembly language program. Since the code generator eliminates the effects of pipeline delay, the scheduler's task is greatly simplified since the scheduler need only maximize the use of the functional units.
摘要翻译：具有代码生成器和调度器的软件编译器。代码生成器将以已知的计算机语言编写的源计算机程序的降低的中间表示（IR）转换为以非标准指令集编写的汇编语言程序。特别地，代码生成器将降低的IR中的向量指令转换成来自非标准指令集的向量指令。定义来自非标准指令集的向量指令，使得用它们编写的汇编语言程序不会受到流水线延迟的影响。因此，根据本发明，当将降低的IR转换成汇编语言程序时，代码生成器消除了流水线延迟的影响。由于代码生成器消除了流水线延迟的影响，因此调度程序的任务大大简化，因为调度程序只需要最大化功能单元的使用。

4. 发明授权

US5347654A System and method for optimizing and generating computer-based code in a parallel processing environment 失效
标题翻译：用于在并行处理环境中优化和生成基于计算机的代码的系统和方法
公开(公告)号：US5347654A
公开(公告)日：1994-09-13
申请号：US830564
申请日：1992-02-03
申请人： Gary W. Sabot , David F. Lively , Alexander D. Vasilevsky
发明人： Gary W. Sabot , David F. Lively , Alexander D. Vasilevsky
IPC分类号： G06F9/45 , G06F15/16
CPC分类号： G06F8/45
摘要： A system and method for optimizing statements to produce more efficient assembly language for use in a parallel processing environment. In doing this, the present invention separates elemental from non-elemental nodes in a statement, encapsulates the elemental statements, and generates a parallel assembly language code stream from encapsulated statements, and a scalar code stream from scalar statements and non-elemental nodes (for which the scalar assembly language is used to utilize a non-elemental resolver).
摘要翻译：一种用于优化语句以在并行处理环境中生成更有效的汇编语言的系统和方法。在这样做时，本发明在语句中分离元素与非元素节点，封装元素语句，并从封装语句和标量语句和非元素节点生成并行汇编语言代码流（用于标量汇编语言用于使用非元素解析器）。

5. 发明授权

US5274818A System and method for compiling a fine-grained array based source program onto a course-grained hardware 失效
标题翻译：将基于细粒度阵列的源程序编译到课程粒度硬件上的系统和方法
公开(公告)号：US5274818A
公开(公告)日：1993-12-28
申请号：US827942
申请日：1992-02-03
申请人： Alexander D. Vasilevsky , Gary W. Sabot , Clifford A. Lasser , Lisa A. Tennies , Tobias M. Weinberg , Linda J. Seamonson
发明人： Alexander D. Vasilevsky , Gary W. Sabot , Clifford A. Lasser , Lisa A. Tennies , Tobias M. Weinberg , Linda J. Seamonson
IPC分类号： G06F9/44 , G06F9/45 , G06F15/80 , G06F9/00
CPC分类号： G06F8/441 , G06F15/8092 , G06F8/443 , G06F8/45
摘要： The present invention provides a parallel vector machine model for building a compiler that exploits three different levels of parallelism found in a variety of parallel processing machines, and in particular, the Connection Machine.RTM. Computer CM-2 system. The fundamental idea behind the parallel vector machine model is to have a target machine that has a collection of thousands of vector processors each with its own interface to memory. Thus allowing a fine-grained array-based source program to be mapped onto a course-grained hardware made up of the vector processors. In the parallel vector machine model used by CM Fortran 1.0, the FPUs, their registers, and the memory hiearchy are directly exposed to the compiler. Thus, the CM-2 target machine is not 64K simple bit-serial processors. Rather, the target is a machine containing 2K PEs (processing elements), where each PE is both superpipelined and superscalar. The compiler uses data distribution to spread the problem out among the 2K processors. A new compiler phase is used to separate the code that runs on the two types of processors in the CM-2; the parallel PEs, which execute a new RISC-like instruction set called PEAC, and the scalar front end processor, which executes SPARC or VAX assembler code. The pipelines in PEs are filled by using vector processing techniques along the PEAC instruction set. A scheduler overlaps the execution of a number of RISC operations.
摘要翻译：本发明提供了一种用于构建编译器的并行向量机模型，其利用在各种并行处理机器，特别是Connection Machine TM计算机CM-2系统中发现的三个不同级别的并行性。并行向量机模型背后的基本思想是拥有一个具有数千个向量处理器的集合的目标机器，每个向量处理器都有自己的内存接口。因此，允许将细粒度的基于阵列的源程序映射到由向量处理器组成的课程粒度的硬件上。在CM Fortran 1.0使用的并行向量机模型中，FPU，其寄存器和内存hiearchy直接暴露给编译器。因此，CM-2目标机不是64K简单的位串行处理器。相反，目标是包含2K PE（处理元件）的机器，其中每个PE都是超级管道和超标量。编译器使用数据分发在2K处理器中传播问题。一个新的编译器阶段用于分离CM-2中两种处理器上运行的代码; 执行称为PEAC的新的类RISC指令集的并行PE和执行SPARC或VAX汇编代码的标量前端处理器。通过使用沿着PEAC指令集的向量处理技术来填充PE中的管道。调度器与许多RISC操作的执行重叠。

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