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    • 1. 发明授权
    • System and method for compiling a fine-grained array based source
program onto a course-grained hardware
    • 将基于细粒度阵列的源程序编译到课程粒度硬件上的系统和方法
    • US5274818A
    • 1993-12-28
    • US827942
    • 1992-02-03
    • Alexander D. VasilevskyGary W. SabotClifford A. LasserLisa A. TenniesTobias M. WeinbergLinda J. Seamonson
    • Alexander D. VasilevskyGary W. SabotClifford A. LasserLisa A. TenniesTobias M. WeinbergLinda J. Seamonson
    • G06F9/44G06F9/45G06F15/80G06F9/00
    • G06F8/441G06F15/8092G06F8/443G06F8/45
    • The present invention provides a parallel vector machine model for building a compiler that exploits three different levels of parallelism found in a variety of parallel processing machines, and in particular, the Connection Machine.RTM. Computer CM-2 system. The fundamental idea behind the parallel vector machine model is to have a target machine that has a collection of thousands of vector processors each with its own interface to memory. Thus allowing a fine-grained array-based source program to be mapped onto a course-grained hardware made up of the vector processors. In the parallel vector machine model used by CM Fortran 1.0, the FPUs, their registers, and the memory hiearchy are directly exposed to the compiler. Thus, the CM-2 target machine is not 64K simple bit-serial processors. Rather, the target is a machine containing 2K PEs (processing elements), where each PE is both superpipelined and superscalar. The compiler uses data distribution to spread the problem out among the 2K processors. A new compiler phase is used to separate the code that runs on the two types of processors in the CM-2; the parallel PEs, which execute a new RISC-like instruction set called PEAC, and the scalar front end processor, which executes SPARC or VAX assembler code. The pipelines in PEs are filled by using vector processing techniques along the PEAC instruction set. A scheduler overlaps the execution of a number of RISC operations.
    • 本发明提供了一种用于构建编译器的并行向量机模型,其利用在各种并行处理机器,特别是Connection Machine TM计算机CM-2系统中发现的三个不同级别的并行性。 并行向量机模型背后的基本思想是拥有一个具有数千个向量处理器的集合的目标机器,每个向量处理器都有自己的内存接口。 因此,允许将细粒度的基于阵列的源程序映射到由向量处理器组成的课程粒度的硬件上。 在CM Fortran 1.0使用的并行向量机模型中,FPU,其寄存器和内存hiearchy直接暴露给编译器。 因此,CM-2目标机不是64K简单的位串行处理器。 相反,目标是包含2K PE(处理元件)的机器,其中每个PE都是超级管道和超标量。 编译器使用数据分发在2K处理器中传播问题。 一个新的编译器阶段用于分离CM-2中两种处理器上运行的代码; 执行称为PEAC的新的类RISC指令集的并行PE和执行SPARC或VAX汇编代码的标量前端处理器。 通过使用沿着PEA​​C指令集的向量处理技术来填充PE中的管道。 调度器与许多RISC操作的执行重叠。
    • 2. 发明授权
    • Compiling a source code vector instruction by generating a subgrid loop
for iteratively processing array elements by plural processing elements
    • 通过生成用于通过多个处理元素反复处理数组元素的子网格循环来编译源代码向量指令
    • US5551039A
    • 1996-08-27
    • US315662
    • 1994-09-30
    • Tobias M. WeinbergLisa A. TenniesAlexander D. Vasilevsky
    • Tobias M. WeinbergLisa A. TenniesAlexander D. Vasilevsky
    • G06F9/45
    • G06F8/445G06F9/30036
    • A software compiler having a code generator and a scheduler. The code generator transforms a lowered intermediate representation (IR) of a source computer program, written in a known computer language, to an assembly language program written in a non-standard instruction set. In particular, the code generator translates vector instructions in the lowered IR to vector instructions from the non-standard instruction set. The vector instructions from the non-standard instruction set are defined such that assembly language programs written with them do not suffer from the effects of pipeline delays. Therefore, according to the present invention, the code generator eliminates the effects of pipeline delays when transforming the lowered IR to the assembly language program. Since the code generator eliminates the effects of pipeline delay, the scheduler's task is greatly simplified since the scheduler need only maximize the use of the functional units.
    • 具有代码生成器和调度器的软件编译器。 代码生成器将以已知的计算机语言编写的源计算机程序的降低的中间表示(IR)转换为以非标准指令集编写的汇编语言程序。 特别地,代码生成器将降低的IR中的向量指令转换成来自非标准指令集的向量指令。 定义来自非标准指令集的向量指令,使得用它们编写的汇编语言程序不会受到流水线延迟的影响。 因此,根据本发明,当将降低的IR转换成汇编语言程序时,代码生成器消除了流水线延迟的影响。 由于代码生成器消除了流水线延迟的影响,因此调度程序的任务大大简化,因为调度程序只需要最大化功能单元的使用。