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1. 发明授权

US09841777B2 Voltage regulator, application-specific integrated circuit and method for providing a load with a regulated voltage 有权
公开(公告)号：US09841777B2
公开(公告)日：2017-12-12
申请号：US14888956
申请日：2013-05-29
申请人： Jerome Enjalbert , Joachim Kruecken , Jalal Ouaddah
发明人： Jerome Enjalbert , Joachim Kruecken , Jalal Ouaddah
IPC分类号： G05F1/59 , G05F1/56 , G05F1/575 , G05F1/565
CPC分类号： G05F1/575 , G05F1/56 , G05F1/565
摘要： A voltage regulator for digital loads combines a closed loop regulation circuit with an open loop topology. A transistor and a bank of transistors share the same voltage source VDD and gate control current. Each of the bank of transistors is sized to match different current load requirements and one or more may be switched in or out as appropriate when the digital load transitions from one operating mode to another. The regulator has good DC load regulation and unconditional stability regardless of output capacitance.

2. 发明授权

US08841946B2 Electronic circuit, safety critical system, and method for providing a reset signal 有权
标题翻译：电子电路，安全关键系统和提供复位信号的方法
公开(公告)号：US08841946B2
公开(公告)日：2014-09-23
申请号：US13810000
申请日：2010-07-20
申请人： Thomas Luedeke , Joachim Kruecken
发明人： Thomas Luedeke , Joachim Kruecken
IPC分类号： H03K4/06 , G06F1/24 , H03L7/00
CPC分类号： H03L7/00 , G06F1/24
摘要： An electronic circuit comprises a reset input for receiving an input reset signal, a clock input for receiving a clock signal, and a reset output for providing an output reset signal. And it comprises a synchronous reset signal path comprising a synchronization unit, arranged to receive the input reset signal and provide the input reset signal synchronized with the clock signal to the reset output when the clock signal is available, and an asynchronous reset signal path arranged to provide the input reset signal to the reset output when a current clock availability information in a clock monitoring signal indicates that the clock signal is not available.
摘要翻译：电子电路包括用于接收输入复位信号的复位输入，用于接收时钟信号的时钟输入和用于提供输出复位信号的复位输出。并且它包括同步复位信号路径，其包括同步单元，布置成当时钟信号可用时接收输入复位信号并将与时钟信号同步的输入复位信号提供给复位输出，并且异步复位信号路径被布置为当时钟监视信号中的当前时钟可用性信息指示时钟信号不可用时，将输入复位信号提供给复位输出。

3. 发明授权

US08519768B2 Clock glitch detection 有权
标题翻译：时钟毛刺检测
公开(公告)号：US08519768B2
公开(公告)日：2013-08-27
申请号：US13148487
申请日：2009-03-31
申请人： Markus Baumeister , Joachim Kruecken , Rolf Schlagenhaft
发明人： Markus Baumeister , Joachim Kruecken , Rolf Schlagenhaft
IPC分类号： H03K3/00
CPC分类号： G06F1/10
摘要： A circuit comprises a clock tree for distributing a clock signal. A first counter is arranged at a first point in the clock tree. Upon detecting a triggering edge in the clock signal, the first counter sets a first current count equal to a first delayed count. After a first delay, the first counter sets the first delayed count equal to the first current count plus an increment. A second counter is arranged at a second point in the clock tree. Upon detecting a triggering edge in the clock signal, the second counter sets a second current count equal to a second delayed count. After a second delay, the second counter sets the second delayed count equal to the second current count plus the increment. A comparator compares the first current count and the second current count. The first point and the second point are not the same, or the second delay is longer than the first delay.
摘要翻译：电路包括用于分配时钟信号的时钟树。第一个计数器被布置在时钟树的第一个点。当检测到时钟信号中的触发边沿时，第一计数器设置等于第一延迟计数的第一当前计数。在第一延迟之后，第一计数器将第一延迟计数设置为等于第一当前计数加上增量。第二个计数器被布置在时钟树的第二个点。在检测到时钟信号中的触发边沿时，第二计数器设置等于第二延迟计数的第二当前计数。在第二延迟之后，第二计数器将第二延迟计数设置为等于第二当前计数加上增量。比较器比较第一当前计数和第二当前计数。第一点和第二点不相同，或者第二个延迟比第一个延迟长。

4. 发明申请

US20130113531A1 ELECTRONIC CIRCUIT, SAFETY CRITICAL SYSTEM, AND METHOD FOR PROVIDING A RESET SIGNAL 有权
标题翻译：电子电路，安全关键系统和提供复位信号的方法
公开(公告)号：US20130113531A1
公开(公告)日：2013-05-09
申请号：US13810000
申请日：2010-07-20
申请人： Thomas Luedeke , Joachim Kruecken
发明人： Thomas Luedeke , Joachim Kruecken
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , G06F1/24
摘要： An electronic circuit comprises a reset input for receiving an input reset signal, a clock input for receiving a clock signal, and a reset output for providing an output reset signal. And it comprises a synchronous reset signal path comprising a synchronization unit, arranged to receive the input reset signal and provide the input reset signal synchronized with the clock signal to the reset output when the clock signal is available, and an asynchronous reset signal path arranged to provide the input reset signal to the reset output when a current clock availability information in a clock monitoring signal indicates that the clock signal is not available.
摘要翻译：电子电路包括用于接收输入复位信号的复位输入，用于接收时钟信号的时钟输入和用于提供输出复位信号的复位输出。并且它包括同步复位信号路径，其包括同步单元，布置成当时钟信号可用时接收输入复位信号并将与时钟信号同步的输入复位信号提供给复位输出，并且异步复位信号路径被布置为当时钟监视信号中的当前时钟可用性信息指示时钟信号不可用时，将输入复位信号提供给复位输出。

5. 发明授权

US08527681B2 Data processing system, data processing method, and apparatus 有权
标题翻译：数据处理系统，数据处理方法和装置
公开(公告)号：US08527681B2
公开(公告)日：2013-09-03
申请号：US12599994
申请日：2007-05-25
申请人： Florian Bogenberger , Joachim Kruecken , Christopher Temple
发明人： Florian Bogenberger , Joachim Kruecken , Christopher Temple
IPC分类号： G06F13/00 , G06F3/00 , G06F11/00
CPC分类号： G06F11/1641 , G06F11/1487 , G06F11/1675 , G06F15/7842 , G06F2201/845
摘要： A data processing system may include a first data path and a second data path. A set of components may include a system component and a partner component, each having a communication interface for communicating data. The components are operable in a synchronized mode and a non-synchronized mode with respect to each other. The set may further include a configuration control system connected to the system component and the partner component, for controlling the set to be in a synchronized mode configuration or a non-synchronized mode configuration. The configuration control system may include a first path selector module connecting the communication interface of the system component to the first data path and the second data path and a partner path selector module connecting the communication interface of the partner component to the first data path and the second data path. The path selector modules may be arranged to enable, depending on the configuration, communication of data to the respective component via one or more selected data path, selected from the first data path and the second data path, and to inhibit communication via the not selected data paths.
摘要翻译：数据处理系统可以包括第一数据路径和第二数据路径。一组组件可以包括系统组件和伙伴组件，每个组件具有用于传送数据的通信接口。组件可以相对于彼此以同步模式和非同步模式操作。该集合还可以包括连接到系统组件和伙伴组件的配置控制系统，用于将组控制为同步模式配置或非同步模式配置。配置控制系统可以包括将系统组件的通信接口连接到第一数据路径和第二数据路径的第一路径选择器模块和将伙伴组件的通信接口连接到第一数据路径的伙伴路径选择器模块，第二条数据路径。路径选择器模块可以被布置成使得根据配置能够经由从第一数据路径和第二数据路径选择的一个或多个所选择的数据路径将数据传送到相应的组件，并且通过未选择的方式禁止通信数据路径。

6. 发明授权

US06166653A System for address initialization of generic nodes in a distributed command and control system and method therefor 有权
公开(公告)号：US06166653A
公开(公告)日：2000-12-26
申请号：US133226
申请日：1998-08-13
申请人： Peter Hans Schulmeyer , Joachim Kruecken , John M. Pigott
发明人： Peter Hans Schulmeyer , Joachim Kruecken , John M. Pigott
IPC分类号： G06F13/14 , B60R21/01 , B60R21/16 , G05B19/042 , G06F15/177 , H04L12/403 , H04Q5/22
CPC分类号： H04L12/10 , G05B19/042 , G05B2219/21028 , G05B2219/25232 , H04L12/403 , H04L2012/40273
摘要： A method and apparatus for assigning unique addresses to each generic "node" in a distributed control system that contains a main controller (52) coupled to a plurality of generic nodes (54) via a distributed communication bus (55). The main controller (52) provides currents and/or voltages to the communication bus (55) via a supply (58). In one embodiment, each node (54) processes the current and voltages to store reference voltages and distance voltages proportional to its distance along the communication bus (55). In another embodiment, each node (54) signals to the main controller (52) when the distance voltage reaches a certain value relative to the reference voltage. The main controller (52) processes the arrival times of these signals to determine a relative distance to each node (54). This distance information is used to assign a unique address to each generic node (54) for identification during normal mode of operation.

7. 发明授权

US09582281B2 Data processing with variable operand size 有权
标题翻译：具有可变操作数大小的数据处理
公开(公告)号：US09582281B2
公开(公告)日：2017-02-28
申请号：US13201077
申请日：2009-03-31
申请人： Joachim Kruecken
发明人： Joachim Kruecken
IPC分类号： G06F9/30
CPC分类号： G06F9/30192 , G06F9/30105 , G06F9/30112
摘要： A method of processing data comprising performing a sequence of operation instructions with variable operand size, wherein respective size codes for different source and destination operands are obtained and registered separately from performing the sequence of operation instructions, and the sequence of operation instructions is performed using operand sizes defined by the registered size codes, the operation instructions of the sequence not themselves containing size codes.
摘要翻译：一种处理数据的方法，包括执行具有可变操作数大小的操作指令序列，其中针对不同的源操作数和目的地操作数的各自的大小代码与执行操作指令序列分开获取和注册，并且使用操作数执行操作指令序列由注册的大小代码定义的大小，序列的操作指令本身不包含大小代码。

8. 发明申请

US20110066779A1 DATA PROCESSING SYSTEM, DATA PROCESSING METHOD, AND APPARATUS 有权
标题翻译：数据处理系统，数据处理方法和装置
公开(公告)号：US20110066779A1
公开(公告)日：2011-03-17
申请号：US12599994
申请日：2007-05-25
申请人： Florian Bogenberger , Joachim Kruecken , Christopher Temple
发明人： Florian Bogenberger , Joachim Kruecken , Christopher Temple
IPC分类号： G06F13/40
CPC分类号： G06F11/1641 , G06F11/1487 , G06F11/1675 , G06F15/7842 , G06F2201/845
摘要： A data processing system may include a first data path and a second data path. A set of components may include a system component and a partner component, each having a communication interface for communicating data. The components are operable in a synchronized mode and a non-synchronized mode with respect to each other. The set may further include a configuration control system connected to the system component and the partner component, for controlling the set to be in a synchronized mode configuration or a non-synchronized mode configuration. The configuration control system may include a first path selector module connecting the communication interface of the system component to the first data path and the second data path and a partner path selector module connecting the communication interface of the partner component to the first data path and the second data path. The path selector modules may be arranged to enable, depending on the configuration, communication of data to the respective component via one or more selected data path, selected from the first data path and the second data path, and to inhibit communication via the not selected data paths.
摘要翻译：数据处理系统可以包括第一数据路径和第二数据路径。一组组件可以包括系统组件和伙伴组件，每个组件具有用于传送数据的通信接口。组件可以相对于彼此以同步模式和非同步模式操作。该集合还可以包括连接到系统组件和伙伴组件的配置控制系统，用于将组控制为同步模式配置或非同步模式配置。配置控制系统可以包括将系统组件的通信接口连接到第一数据路径和第二数据路径的第一路径选择器模块和将伙伴组件的通信接口连接到第一数据路径的伙伴路径选择器模块，第二条数据路径。路径选择器模块可以被布置成使得根据配置能够经由从第一数据路径和第二数据路径选择的一个或多个所选择的数据路径将数据传送到相应的组件，并且通过未选择的方式禁止通信数据路径。

9. 发明申请

US20120151189A1 DATA PROCESSING WITH VARIABLE OPERAND SIZE 有权
标题翻译：具有可变操作尺寸的数据处理
公开(公告)号：US20120151189A1
公开(公告)日：2012-06-14
申请号：US13201077
申请日：2009-03-31
申请人： Joachim Kruecken
发明人： Joachim Kruecken
IPC分类号： G06F9/30 , G06F9/34 , G06F9/312
CPC分类号： G06F9/30192 , G06F9/30105 , G06F9/30112
摘要： A method of processing data comprising performing a sequence of operation instructions with variable operand size, wherein respective size codes for different source and destination operands are obtained and registered separately from performing the sequence of operation instructions, and the sequence of operation instructions is performed using operand sizes defined by the registered size codes, the operation instructions of the sequence not themselves containing size codes.
摘要翻译：一种处理数据的方法，包括执行具有可变操作数大小的操作指令序列，其中针对不同的源操作数和目的地操作数的各自的大小代码与执行操作指令序列分开获取和注册，并且使用操作数执行操作指令序列由注册的大小代码定义的大小，序列的操作指令本身不包含大小代码。

10. 发明授权

US08131914B2 Electronic device having a memory element and method of operation therefor 有权
标题翻译：具有存储元件的电子设备及其操作方法
公开(公告)号：US08131914B2
公开(公告)日：2012-03-06
申请号：US12278438
申请日：2006-02-09
申请人： Joachim Kruecken
发明人： Joachim Kruecken
IPC分类号： G06F12/00
CPC分类号： G06F13/1668
摘要： An electronic device comprises a processing unit operably coupled to a buffer random access memory, in turn operably coupled to a non-volatile memory configured to emulate an electrically erasable programmable read only memory. The processing unit is arranged to transfer data between the buffer RAM and the non-volatile memory at a first clock frequency. A second RAM is operably coupled between the processing unit and the non-volatile memory and the processing unit sets a Tag bit in the second RAM to identify an address in the buffer RAM that is being written to or read from by the processing unit.
摘要翻译：电子设备包括可操作地耦合到缓冲器随机存取存储器的处理单元，所述缓冲器随机存取存储器又可操作地耦合到被配置为模拟电可擦除可编程只读存储器的非易失性存储器。处理单元被布置成以第一时钟频率在缓冲RAM和非易失性存储器之间传送数据。第二RAM可操作地耦合在处理单元和非易失性存储器之间，并且处理单元设置第二RAM中的标签位，以识别缓冲RAM中正被写入或从处理单元读取的地址。

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