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1. 发明授权

US07586802B2 Memory, bit-line pre-charge circuit and bit-line pre-charge method 有权
标题翻译：存储器，位线预充电电路和位线预充电方法
公开(公告)号：US07586802B2
公开(公告)日：2009-09-08
申请号：US12027333
申请日：2008-02-07
申请人： Jer-Hau Hsu , Fu-Nian Liang , Yufe-Feng Lin
发明人： Jer-Hau Hsu , Fu-Nian Liang , Yufe-Feng Lin
IPC分类号： G11C7/00
CPC分类号： G11C7/12
摘要： A memory is provided. The memory includes a memory cell, a clamp transistor, an inverter, a bit line, a pre-charge path and a detector and controller circuit. The memory is coupled to the clamp transistor. The clamp transistor has a first end, a second end and a control end. The inverter has an input end electrically connected to the second end of the clamp transistor and an output end electrically connected to the control end of the clamp transistor. The bit line is electrically connected to the second end of the clamp transistor and the input end of the inverter and has a bit-line voltage thereon. The pre-charge path is electrically connected to the first end of the clamp transistor through a node having a sensing voltage thereon. The detector and controller circuit is electrically connected to the first end of the clamp transistor and the pre-charge path for detecting the sensing voltage in order to open the pre-charge path to raise the bit-line voltage when the sensing voltage is at a low level and close the pre-charge path when the sensing voltage is at a high level.
摘要翻译：提供记忆。存储器包括存储单元，钳位晶体管，反相器，位线，预充电路径以及检测器和控制器电路。存储器耦合到钳位晶体管。钳位晶体管具有第一端，第二端和控制端。逆变器具有电连接到钳位晶体管的第二端的输入端和电连接到钳位晶体管的控制端的输出端。位线电连接到钳位晶体管的第二端和反相器的输入端，并在其上具有位线电压。预充电路径通过其上具有感测电压的节点电连接到钳位晶体管的第一端。检测器和控制器电路电连接到钳位晶体管的第一端和用于检测感测电压的预充电路径，以便当感测电压为一个时，打开预充电路径以升高位线电压低电平并且当感测电压处于高电平时闭合预充电路径。

2. 发明申请

US20090201747A1 MEMORY, BIT-LINE PRE-CHARGE CIRCUIT AND BIT-LINE PRE-CHARGE METHOD 有权
标题翻译：存储器，位线预充电电路和位线预充电方法
公开(公告)号：US20090201747A1
公开(公告)日：2009-08-13
申请号：US12027333
申请日：2008-02-07
申请人： Jer-Hau Hsu , Fu-Nian Liang , Yufe-Feng Lin
发明人： Jer-Hau Hsu , Fu-Nian Liang , Yufe-Feng Lin
IPC分类号： G11C7/00
CPC分类号： G11C7/12
摘要： A memory is provided. The memory includes a memory cell, a clamp transistor, an inverter, a bit line, a pre-charge path and a detector and controller circuit. The memory is coupled to the clamp transistor. The clamp transistor has a first end, a second end and a control end. The inverter has an input end electrically connected to the second end of the clamp transistor and an output end electrically connected to the control end of the clamp transistor. The bit line is electrically connected to the second end of the clamp transistor and the input end of the inverter and has a bit-line voltage thereon. The pre-charge path is electrically connected to the first end of the clamp transistor through a node having a sensing voltage thereon. The detector and controller circuit is electrically connected to the first end of the clamp transistor and the pre-charge path for detecting the sensing voltage in order to open the pre-charge path to raise the bit-line voltage when the sensing voltage is at a low level and close the pre-charge path when the sensing voltage is at a high level.
摘要翻译：提供记忆。存储器包括存储单元，钳位晶体管，反相器，位线，预充电路径以及检测器和控制器电路。存储器耦合到钳位晶体管。钳位晶体管具有第一端，第二端和控制端。逆变器具有电连接到钳位晶体管的第二端的输入端和电连接到钳位晶体管的控制端的输出端。位线电连接到钳位晶体管的第二端和反相器的输入端，并在其上具有位线电压。预充电路径通过其上具有感测电压的节点电连接到钳位晶体管的第一端。检测器和控制器电路电连接到钳位晶体管的第一端和用于检测感测电压的预充电路径，以便当感测电压为一个时，打开预充电路径以升高位线电压低电平并且当感测电压处于高电平时闭合预充电路径。

3. 发明授权

US06449191B1 Current-mode sense amplifier with low power consumption 有权
标题翻译：电流模式读出放大器功耗低
公开(公告)号：US06449191B1
公开(公告)日：2002-09-10
申请号：US10063137
申请日：2002-03-25
申请人： Hong-Chin Lin , Fu-Nian Liang , Ching-Yuan Lin
发明人： Hong-Chin Lin , Fu-Nian Liang , Ching-Yuan Lin
IPC分类号： G11C1606
CPC分类号： G11C7/062 , G11C16/28 , G11C2207/063
摘要： A current-mode sense amplifier for detecting data stored in a flash memory cell. The sense amplifier has a first current generator for generating a first current to a first circuit according to current flowing out of the memory cell, a second current generator for generating a second current to a second circuit according to current flowing out of a reference cell, and a switch. When the switch is on and a common node of the first circuit and the second circuit is floating, the first and second circuits will generate equal initial voltages. When the switch is off and the common node of the first and second circuits is grounded, one of the initial voltages will increase, and the other initial voltage will decrease.
摘要翻译：一种用于检测存储在闪存单元中的数据的电流模式读出放大器。读出放大器具有第一电流发生器，用于根据流过存储单元的电流向第一电路产生第一电流;第二电流发生器，用于根据从参考单元流出的电流产生第二电流到第二电路; 和开关。当开关导通并且第一电路和第二电路的公共节点浮动时，第一和第二电路将产生相等的初始电压。当开关关闭并且第一和第二电路的公共节点接地时，初始电压之一将增加，另一个初始电压将降低。

4. 发明授权

US07826275B2 Memory circuit with high reading speed and low switching noise 有权
标题翻译：具有高读取速度和低开关噪声的存储电路
公开(公告)号：US07826275B2
公开(公告)日：2010-11-02
申请号：US11953161
申请日：2007-12-10
申请人： Yung-Hsu Chen , Chun-Yu Liao , Chia-Jung Chen , Fu-Nian Liang
发明人： Yung-Hsu Chen , Chun-Yu Liao , Chia-Jung Chen , Fu-Nian Liang
IPC分类号： G11C16/04
CPC分类号： G11C7/02 , G11C7/1051 , G11C7/1057
摘要： A memory circuit with relatively high reading speed and relatively low switching noise is provided. The memory circuit includes an output buffer device having a first input receiving a data signal having a first voltage level, a second input receiving a pre-set voltage having a second voltage level and an output outputting the data signal, and a pre-set circuit constructed by a pair of MOSFETs and providing the pre-set voltage to the second input before the output buffer device receives the data signal. The pre-set circuit receives a control signal activating the pair of MOSFETs at the same time, and when the output buffer device receives the data signal, a voltage level of the second input is swung from the second level to the first voltage level.
摘要翻译：提供了具有相对高的读取速度和相对低的开关噪声的存储器电路。存储器电路包括输出缓冲器件，其具有接收具有第一电压电平的数据信号的第一输入端，接收具有第二电压电平的预置电压的第二输入端和输出数据信号的输出端，以及预置电路由一对MOSFET构成，并且在输出缓冲器件接收数据信号之前将预设电压提供给第二输入端。预置电路同时接收到激活该对MOSFET的控制信号，并且当输出缓冲器件接收到数据信号时，第二输入的电压电平从第二电平摆动到第一电压电平。

5. 发明申请

US20090147591A1 MEMORY CIRCUIT WITH HIGH READING SPEED AND LOW SWITCHING NOISE 有权
标题翻译：具有高读取速度和低开关噪声的存储器电路
公开(公告)号：US20090147591A1
公开(公告)日：2009-06-11
申请号：US11953161
申请日：2007-12-10
申请人： Yung-Hsu Chen , Chun-Yu Liao , Chia-Jung Chen , Fu-Nian Liang
发明人： Yung-Hsu Chen , Chun-Yu Liao , Chia-Jung Chen , Fu-Nian Liang
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C7/02 , G11C7/1051 , G11C7/1057
摘要： A memory circuit with relatively high reading speed and relatively low switching noise is provided. The memory circuit includes an output buffer device having a first input receiving a data signal having a first voltage level, a second input receiving a pre-set voltage having a second voltage level and an output outputting the data signal, and a pre-set circuit constructed by a pair of MOSFETs and providing the pre-set voltage to the second input before the output buffer device receives the data signal. The pre-set circuit receives a control signal activating the pair of MOSFETs at the same time, and when the output buffer device receives the data signal, a voltage level of the second input is swung from the second level to the first voltage level.
摘要翻译：提供了具有相对高的读取速度和相对低的开关噪声的存储器电路。存储器电路包括输出缓冲器件，其具有接收具有第一电压电平的数据信号的第一输入端，接收具有第二电压电平的预置电压的第二输入端和输出数据信号的输出端，以及预置电路由一对MOSFET构成，并且在输出缓冲器件接收数据信号之前将预设电压提供给第二输入端。预置电路同时接收到激活该对MOSFET的控制信号，并且当输出缓冲器件接收到数据信号时，第二输入的电压电平从第二电平摆动到第一电压电平。

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