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1. 发明申请

US20120117283A1 ARRANGEMENT COMPRISING A FIRST SEMICONDUCTOR CHIP AND A SECOND SEMICONDUCTOR CHIP CONNECTED THERETO 有权
标题翻译：包含第一半导体芯片和连接的第二个半导体芯片的布置
公开(公告)号：US20120117283A1
公开(公告)日：2012-05-10
申请号：US13355130
申请日：2012-01-20
申请人： Jens Barrenscheen , Peter Rohm , Angela Rohm , Hannes Estl , Axel Aue , Jens Graf , Herman Roozenbeek
发明人： Jens Barrenscheen , Peter Rohm , Angela Rohm , Hannes Estl , Axel Aue , Jens Graf , Herman Roozenbeek
IPC分类号： G06F3/00
CPC分类号： G05B19/0428 , G05B9/02 , G05B2219/25012
摘要： A data communication method for semiconductor chips including transmitting load control data, pilot data and a transmission clock signal from a first semiconductor chip to one or more second semiconductor chips that are each coupled to one or more electrical loads, driving the electrical loads based on a timing defined by the load control data, deriving a transmission rate by dividing the transmission clock signal by a division factor prescribed by the pilot data, and transmitting diagnostic data at the transmission rate from the one or more second semiconductor chips to the first semiconductor chip.
摘要翻译：一种用于半导体芯片的数据通信方法，包括从第一半导体芯片向一个或多个第二半导体芯片发送负载控制数据，导频数据和传输时钟信号，所述第二半导体芯片分别耦合到一个或多个电负载，基于由负载控制数据定义的定时，通过将传输时钟信号除以由导频数据规定的分频因子得出传输速率，并以传输速率从一个或多个第二半导体芯片向第一半导体芯片发送诊断数据。

2. 发明授权

US08112563B2 Arrangement comprising a first semiconductor chip and a second semiconductor chip connected thereto 有权
标题翻译：包括第一半导体芯片和与其连接的第二半导体芯片的布置
公开(公告)号：US08112563B2
公开(公告)日：2012-02-07
申请号：US10727102
申请日：2003-12-02
申请人： Jens Barrenscheen , Peter Rohm , Angela Rohm, legal representative , Hannes Estl , Axel Aue , Jens Graf , Herman Roozenbeek
发明人： Jens Barrenscheen , Peter Rohm , Hannes Estl , Axel Aue , Jens Graf , Herman Roozenbeek
IPC分类号： G06F13/12 , G06F13/38
CPC分类号： G05B19/0428 , G05B9/02 , G05B2219/25012
摘要： An arrangement including a first semiconductor chip and a second semiconductor chip connected thereto, where the second semiconductor chip is additionally connected to electrical loads and drives these electrical loads on the basis of a timing which is prescribed to it by load control data, and where the first semiconductor chip transmits to the second semiconductor chip the aforementioned load control data and pilot data which control the second semiconductor chip, and where the second semiconductor chip transmits to the first semiconductor chip diagnostic data which represent states prevailing in the second semiconductor chip or events which occur. The diagnostic data are transmitted via a first transmission channel and the load control data and the pilot data are transmitted via a second transmission channel.
摘要翻译：一种包括连接到其上的第一半导体芯片和第二半导体芯片的布置，其中第二半导体芯片另外连接到电负载并且基于由负载控制数据规定的定时驱动这些电负载，并且其中第一半导体芯片向第二半导体芯片发送上述负载控制数据和控制第二半导体芯片的导频数据，第二半导体芯片向第一半导体芯片发送表示第二半导体芯片中的状态的诊断数据，发生。诊断数据经由第一传输信道发送，负载控制数据和导频数据经由第二传输信道发送。

3. 发明授权

US07738588B2 Arrangement comprising a first semiconductor chip and a second semiconductor chip connected thereto 有权
标题翻译：包括第一半导体芯片和与其连接的第二半导体芯片的布置
公开(公告)号：US07738588B2
公开(公告)日：2010-06-15
申请号：US10727108
申请日：2003-12-02
申请人： Jens Barrenscheen , Peter Rohm , Angela Rohm, legal representative , Axel Aue , Jens Graf , Herman Roozenbeek
发明人： Jens Barrenscheen , Peter Rohm , Axel Aue , Jens Graf , Herman Roozenbeek
IPC分类号： H04L27/00
CPC分类号： H04L1/24 , G05B2219/2202 , G05B2219/2214 , G05B2219/24044 , G05B2219/24065
摘要： An arrangement including a first semiconductor chip and a second semiconductor chip connected thereto, where the second semiconductor chip is additionally connected to electrical loads and drives these electrical loads on the basis of a timing which is prescribed to it by load control data, and where the first semiconductor chip transmits to the second semiconductor chip the aforementioned load control data and pilot data which control the second semiconductor chip, and where the second semiconductor chip transmits to the first semiconductor chip diagnostic data which represent states prevailing in the second semiconductor chip or events which occur. The first semiconductor chip transmits appropriate pilot data in order to prescribe to the second semiconductor chip what transmission rate is to be used by the second semiconductor chip to transmit the diagnostic data to the first semiconductor chip.
摘要翻译：一种包括连接到其上的第一半导体芯片和第二半导体芯片的布置，其中第二半导体芯片另外连接到电负载并且基于由负载控制数据规定的定时驱动这些电负载，并且其中第一半导体芯片向第二半导体芯片发送上述负载控制数据和控制第二半导体芯片的导频数据，第二半导体芯片向第一半导体芯片发送表示第二半导体芯片中的状态的诊断数据，发生。第一半导体芯片发送适当的导频数据，以便向第二半导体芯片规定第二半导体芯片将使用什么传输速率将诊断数据发送到第一半导体芯片。

4. 发明授权

US08380899B2 Arrangement comprising a first semiconductor chip and a second semiconductor chip connected thereto 有权
标题翻译：包括第一半导体芯片和与其连接的第二半导体芯片的布置
公开(公告)号：US08380899B2
公开(公告)日：2013-02-19
申请号：US13355130
申请日：2012-01-20
申请人： Jens Barrenscheen , Hannes Estl , Axel Aue , Jens Graf , Hermann Roozenbeek , Angela Rohm
发明人： Jens Barrenscheen , Peter Rohm , Hannes Estl , Axel Aue , Jens Graf , Hermann Roozenbeek
IPC分类号： G06F13/12 , G06F13/38
CPC分类号： G05B19/0428 , G05B9/02 , G05B2219/25012
摘要： A data communication method for semiconductor chips including transmitting load control data, pilot data and a transmission clock signal from a first semiconductor chip to one or more second semiconductor chips that are each coupled to one or more electrical loads, driving the electrical loads based on a timing defined by the load control data, deriving a transmission rate by dividing the transmission clock signal by a division factor prescribed by the pilot data, and transmitting diagnostic data at the transmission rate from the one or more second semiconductor chips to the first semiconductor chip.
摘要翻译：一种用于半导体芯片的数据通信方法，包括从第一半导体芯片向一个或多个第二半导体芯片发送负载控制数据，导频数据和传输时钟信号，所述第二半导体芯片分别耦合到一个或多个电负载，基于由负载控制数据定义的定时，通过将传输时钟信号除以由导频数据规定的分频因子得出传输速率，并以传输速率从一个或多个第二半导体芯片向第一半导体芯片发送诊断数据。

5. 发明授权

US07418566B2 Memory arrangement and method for reading from a memory arrangement 有权
标题翻译：用于从存储器布置读取的存储器布置和方法
公开(公告)号：US07418566B2
公开(公告)日：2008-08-26
申请号：US10079767
申请日：2002-02-19
申请人： Jens Graf , Martin Thomas , Axel Aue
发明人： Jens Graf , Martin Thomas , Axel Aue
IPC分类号： G06F13/14
CPC分类号： G11C7/1051 , G06F12/0893 , G11C7/103 , G11C16/24 , G11C16/26 , G11C2207/2245
摘要： A memory arrangement is provided, which has a programmable memory and a first buffer memory associated with the programmable memory, to which buffer memory, in the case of a command access, at least one command following the accessed command is written. A second buffer memory may also be provided, to which buffer memory, in the case of a data access, at least one datum following the accessed datum is written. Also provided is a method for reading from a memory arrangement during program execution, wherein presence of a command access or a data access recognized, and a command following the accessed command is written to a first buffer memory and a datum following the accessed datum is written to a second buffer memory. Thus, in this manner, a separate buffer memory is described for data accesses, and thus the content of the buffer for command accesses is not overwritten or destroyed when data accesses occur during the program execution.
摘要翻译：提供了一种存储器装置，其具有可编程存储器和与可编程存储器相关联的第一缓冲存储器，在命令访问的情况下，缓冲存储器写入至少一个跟随所访问命令的命令。还可以提供第二缓冲存储器，在数据存取的情况下，缓冲存储器被写入跟随访问的数据的至少一个数据。还提供了一种用于在程序执行期间从存储器装置读取的方法，其中识别的命令访问或数据访问的存在以及被访问命令之后的命令被写入到第一缓冲存储器，并且写入访问的数据之后的数据被写入到第二缓冲存储器。因此，以这种方式，描述了用于数据访问的单独的缓冲存储器，因此当在程序执行期间发生数据访问时，用于命令访问的缓冲器的内容不被覆盖或破坏。

6. 发明授权

US06765829B2 Device having a memory element, and a memory element 失效
标题翻译：具有存储元件的装置和存储元件
公开(公告)号：US06765829B2
公开(公告)日：2004-07-20
申请号：US10075851
申请日：2002-02-13
申请人： Jens Graf , Martin Thomas , Axel Aue
发明人： Jens Graf , Martin Thomas , Axel Aue
IPC分类号： G11C800
CPC分类号： G11C7/1084 , G06F13/4243 , G11C7/1078
摘要： A memory element and a device having a processor and a memory element, the memory element being positioned outside of the processor and being connectible to a processor via address and/or data lines, the address and/or data lines are each configured in an LVDS structure having corresponding drivers and receivers, and the drivers and receivers each being integrated in the memory element or in the processor.
摘要翻译：存储元件和具有处理器和存储器元件的器件，存储器元件位于处理器外部并且可经由地址和/或数据线与处理器连接，地址和/或数据线各自配置为LVDS 结构具有相应的驱动器和接收器，并且驱动器和接收器各自被集成在存储器元件中或处理器中。

7. 发明授权

US09740584B2 Method and device for testing a computer core in a processor having at least two computer cores 有权
公开(公告)号：US09740584B2
公开(公告)日：2017-08-22
申请号：US13124445
申请日：2009-09-03
申请人： Bernd Mueller , Axel Aue
发明人： Bernd Mueller , Axel Aue
IPC分类号： G06F11/22
CPC分类号： G06F11/2236
摘要： A method and a device for testing a computer core in a processor having at least two computer cores is described. The computer cores are connected to each other via an internal connecting system, both computer cores contributing toward the operating sequence of a machine. In the method for testing a computer core, with which a high error detection rate may be achieved in a minimum outlay of time, a test is run in one computer core, while a program for executing the driving operation of the motor vehicle is being processed in the other computer core at the same time.

8. 发明授权

US09176523B2 Active functional limiting of a microcontroller 有权
标题翻译：微控制器的主动功能限制
公开(公告)号：US09176523B2
公开(公告)日：2015-11-03
申请号：US13914264
申请日：2013-06-10
申请人： Axel Aue , Matthias Schreiber
发明人： Axel Aue , Matthias Schreiber
IPC分类号： G06F1/06 , F02D41/26 , G06F13/12 , G06F21/00 , G06F21/74 , F02D41/28
CPC分类号： G06F1/06 , F02D41/26 , F02D41/28 , F02D2041/286 , G06F13/12 , G06F21/00 , G06F21/74
摘要： A microcontroller for use in a control device for an internal combustion engine includes: an analysis access via which internal data in the microcontroller can be accessed from outside the microcontroller; a clock generator which generates clock timing for data communication of the microcontroller with other units. The microcontroller is configured to change over from a first clock to a second clock when there is an access to the microcontroller via the analysis access.
摘要翻译：用于内燃机的控制装置的微控制器包括：分析存取器，通过该分析存取器可以从微控制器外部访问微控制器中的内部数据; 时钟发生器，其产生用于与其他单元的微控制器的数据通信的时钟定时。微控制器配置为通过分析访问访问微控制器时，从第一个时钟切换到第二个时钟。

9. 发明授权

US08731737B2 Microcontroller having a computing unit and a logic circuit, and method for carrying out computations by a microcontroller for a regulation or a control in a vehicle 有权
标题翻译：具有计算单元和逻辑电路的微控制器以及用于由微控制器进行用于车辆中的调节或控制的计算的方法
公开(公告)号：US08731737B2
公开(公告)日：2014-05-20
申请号：US13093421
申请日：2011-04-25
申请人： Felix Streichert , Tobias Lang , Heiner Markert , Axel Aue , Thomas Kruse , Udo Schulz , Thomas Richardsen , Michael Saetzler , Ulrich Schulmeister , Nico Bannow , Holger Ulmer , Matthias Schreiber
发明人： Felix Streichert , Tobias Lang , Heiner Markert , Axel Aue , Thomas Kruse , Udo Schulz , Thomas Richardsen , Michael Saetzler , Ulrich Schulmeister , Nico Bannow , Holger Ulmer , Matthias Schreiber
IPC分类号： G06F19/00 , G06F7/00
CPC分类号： F02D41/28 , F02D41/2422
摘要： A microcontroller having a computing unit and a logic circuit. The microcontroller carries out computations for a regulation or control in a vehicle. The computing unit is connected to the logic circuit, and the logic circuit has an arrangement for computing an exponential function and is configurable.
摘要翻译：具有计算单元和逻辑电路的微控制器。微控制器执行车辆中的调节或控制的计算。计算单元连接到逻辑电路，并且逻辑电路具有用于计算指数函数并且是可配置的布置。

10. 发明申请

US20090083463A1 Method for Transmitting Data From and to a Control Device 有权
标题翻译：从控制设备传输数据的方法
公开(公告)号：US20090083463A1
公开(公告)日：2009-03-26
申请号：US12226703
申请日：2007-04-19
申请人： Axel Aue
发明人： Axel Aue
IPC分类号： G06F13/42 , F02D45/00
CPC分类号： H04L12/40032 , H04L2012/40215 , H04L2012/40273
摘要： A method for transmitting data from and to a control device, in particular an engine control device for a motor vehicle that has a first communication interface and a second communication interface, the method having the following steps: connecting the first communication interface to a development tool, and connecting the second communication interface to one or more function units during the development phase of the control device, transmitting data from the control device to the development tool via the first communication interface using a first communication protocol, transmitting data from the development tool to the control device via the first communication interface using the first communication protocol, breaking the connection between the first communication interface and the development tool, connecting the first communication interface to one or more additional 20 function units, and transmitting data between the control device and the other function unit or function units via the first communication interface using a second communication protocol.
摘要翻译：一种用于从控制装置，特别是具有第一通信接口和第二通信接口的机动车辆的发动机控制装置发送数据的方法，该方法具有以下步骤：将第一通信接口连接到开发工具并且在所述控制装置的开发阶段将所述第二通信接口连接到一个或多个功能单元，使用第一通信协议经由所述第一通信接口从所述控制装置向所述开发工具发送数据，将数据从所述开发工具传送到所述控制装置经由所述第一通信接口使用所述第一通信协议，破坏所述第一通信接口和所述开发工具之间的连接，将所述第一通信接口连接到一个或多个附加的20个功能单元，以及在所述控制设备和所述控制设备之间传送数据其他功能单元或功能单元经由第一通信接口使用第二通信协议。

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