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1. 发明授权

US08380899B2 Arrangement comprising a first semiconductor chip and a second semiconductor chip connected thereto 有权
标题翻译：包括第一半导体芯片和与其连接的第二半导体芯片的布置
公开(公告)号：US08380899B2
公开(公告)日：2013-02-19
申请号：US13355130
申请日：2012-01-20
申请人： Jens Barrenscheen , Hannes Estl , Axel Aue , Jens Graf , Hermann Roozenbeek , Angela Rohm
发明人： Jens Barrenscheen , Peter Rohm , Hannes Estl , Axel Aue , Jens Graf , Hermann Roozenbeek
IPC分类号： G06F13/12 , G06F13/38
CPC分类号： G05B19/0428 , G05B9/02 , G05B2219/25012
摘要： A data communication method for semiconductor chips including transmitting load control data, pilot data and a transmission clock signal from a first semiconductor chip to one or more second semiconductor chips that are each coupled to one or more electrical loads, driving the electrical loads based on a timing defined by the load control data, deriving a transmission rate by dividing the transmission clock signal by a division factor prescribed by the pilot data, and transmitting diagnostic data at the transmission rate from the one or more second semiconductor chips to the first semiconductor chip.
摘要翻译：一种用于半导体芯片的数据通信方法，包括从第一半导体芯片向一个或多个第二半导体芯片发送负载控制数据，导频数据和传输时钟信号，所述第二半导体芯片分别耦合到一个或多个电负载，基于由负载控制数据定义的定时，通过将传输时钟信号除以由导频数据规定的分频因子得出传输速率，并以传输速率从一个或多个第二半导体芯片向第一半导体芯片发送诊断数据。

2. 发明申请

US20120117283A1 ARRANGEMENT COMPRISING A FIRST SEMICONDUCTOR CHIP AND A SECOND SEMICONDUCTOR CHIP CONNECTED THERETO 有权
标题翻译：包含第一半导体芯片和连接的第二个半导体芯片的布置
公开(公告)号：US20120117283A1
公开(公告)日：2012-05-10
申请号：US13355130
申请日：2012-01-20
申请人： Jens Barrenscheen , Peter Rohm , Angela Rohm , Hannes Estl , Axel Aue , Jens Graf , Herman Roozenbeek
发明人： Jens Barrenscheen , Peter Rohm , Angela Rohm , Hannes Estl , Axel Aue , Jens Graf , Herman Roozenbeek
IPC分类号： G06F3/00
CPC分类号： G05B19/0428 , G05B9/02 , G05B2219/25012
摘要： A data communication method for semiconductor chips including transmitting load control data, pilot data and a transmission clock signal from a first semiconductor chip to one or more second semiconductor chips that are each coupled to one or more electrical loads, driving the electrical loads based on a timing defined by the load control data, deriving a transmission rate by dividing the transmission clock signal by a division factor prescribed by the pilot data, and transmitting diagnostic data at the transmission rate from the one or more second semiconductor chips to the first semiconductor chip.
摘要翻译：一种用于半导体芯片的数据通信方法，包括从第一半导体芯片向一个或多个第二半导体芯片发送负载控制数据，导频数据和传输时钟信号，所述第二半导体芯片分别耦合到一个或多个电负载，基于由负载控制数据定义的定时，通过将传输时钟信号除以由导频数据规定的分频因子得出传输速率，并以传输速率从一个或多个第二半导体芯片向第一半导体芯片发送诊断数据。

3. 发明授权

US08112563B2 Arrangement comprising a first semiconductor chip and a second semiconductor chip connected thereto 有权
标题翻译：包括第一半导体芯片和与其连接的第二半导体芯片的布置
公开(公告)号：US08112563B2
公开(公告)日：2012-02-07
申请号：US10727102
申请日：2003-12-02
申请人： Jens Barrenscheen , Peter Rohm , Angela Rohm, legal representative , Hannes Estl , Axel Aue , Jens Graf , Herman Roozenbeek
发明人： Jens Barrenscheen , Peter Rohm , Hannes Estl , Axel Aue , Jens Graf , Herman Roozenbeek
IPC分类号： G06F13/12 , G06F13/38
CPC分类号： G05B19/0428 , G05B9/02 , G05B2219/25012
摘要： An arrangement including a first semiconductor chip and a second semiconductor chip connected thereto, where the second semiconductor chip is additionally connected to electrical loads and drives these electrical loads on the basis of a timing which is prescribed to it by load control data, and where the first semiconductor chip transmits to the second semiconductor chip the aforementioned load control data and pilot data which control the second semiconductor chip, and where the second semiconductor chip transmits to the first semiconductor chip diagnostic data which represent states prevailing in the second semiconductor chip or events which occur. The diagnostic data are transmitted via a first transmission channel and the load control data and the pilot data are transmitted via a second transmission channel.
摘要翻译：一种包括连接到其上的第一半导体芯片和第二半导体芯片的布置，其中第二半导体芯片另外连接到电负载并且基于由负载控制数据规定的定时驱动这些电负载，并且其中第一半导体芯片向第二半导体芯片发送上述负载控制数据和控制第二半导体芯片的导频数据，第二半导体芯片向第一半导体芯片发送表示第二半导体芯片中的状态的诊断数据，发生。诊断数据经由第一传输信道发送，负载控制数据和导频数据经由第二传输信道发送。

4. 发明申请

US20110074493A1 CONFIGURABLE NP CHANNEL LATERAL DRAIN EXTENDED MOS-BASED TRANSISTOR 有权
标题翻译：可配置的NP通道横向引入扩展的MOS晶体管
公开(公告)号：US20110074493A1
公开(公告)日：2011-03-31
申请号：US12883726
申请日：2010-09-16
申请人： Marie Denison , Hannes Estl
发明人： Marie Denison , Hannes Estl
IPC分类号： G05F1/10 , H01L29/78 , H01L21/8238
CPC分类号： H01L27/092 , H01L29/0634 , H01L29/0653 , H01L29/402 , H01L29/404 , H01L29/407 , H01L29/7816 , H01L29/7824 , H01L29/7831 , H01L29/7834 , H01L29/7835 , H01L29/7846
摘要： An integrated circuit containing a configurable dual n/p-channel 3-D resurf high voltage MOS field effect transistor (MOSFET) is disclosed. An n-channel drain is coterminous with a p-channel source in an n-well, and a p-channel drain is coterminous with an n-channel source in a p-well. A lateral drift region including n-type drift lanes and p-type drift lanes extends between the n and p wells. A resurf layer abuts the lateral drift region. The n-channel MOS gate is separate from the p-channel MOS gate. The p-channel MOS gate may be operated as a field plate in the n-channel mode, and vice versa. An n-channel MOS transistor may be integrated into the n-channel MOS source to provide an n-channel cascode transistor configuration, and similarly for a p-channel cascode configuration, to debias parasitic bipolar transistors under the MOS gates. Circuits using the MOSFET with various loads are also disclosed.
摘要翻译：公开了一种包含可配置的双n / p沟道3-D复用高压MOS场效应晶体管（MOSFET）的集成电路。 n沟道漏极在n阱中与p沟道源相邻，并且p沟道漏极与p阱中的n沟道源相邻。包括n型漂移通道和p型漂移通道的横向漂移区域在n阱和p阱之间延伸。再生层邻接横向漂移区域。 n沟道MOS栅极与p沟道MOS栅极分离。 p沟道MOS栅极可以作为n沟道模式中的场板操作，反之亦然。 n沟道MOS晶体管可以被集成到n沟道MOS源中以提供n沟道共源共栅晶体管配置，并且类似地用于p沟道共源共栅配置，以在MOS栅极之下去除寄生双极晶体管。还公开了使用具有各种负载的MOSFET的电路。

5. 发明授权

US07253474B2 Quasi-vertical semiconductor component 有权
标题翻译：准垂直半导体元件
公开(公告)号：US07253474B2
公开(公告)日：2007-08-07
申请号：US10667629
申请日：2003-09-22
申请人： Marie Denison , Hannes Estl
发明人： Marie Denison , Hannes Estl
IPC分类号： H01L27/01
CPC分类号： H01L29/7811 , H01L29/0684 , H01L29/0688 , H01L29/0804 , H01L29/1004 , H01L29/1095 , H01L29/7322 , H01L29/7802
摘要： A quasi-vertical semiconductor component in which, by variation of the layout, the process or the wiring of inner cells, a compensation for a voltage drop along a buried layer is provided in order thus to ensure a similar operating point of the individual inner cells in the well. Therefore, the disadvantages brought about by a voltage drop in the buried layer are ultimately overcome.
摘要翻译：准垂直半导体元件，其中通过布局的变化，内部单元的处理或布线，沿着掩埋层提供对电压降的补偿，从而确保各个内部单元的类似工作点在井里。因此，最终克服了埋层中的电压降引起的缺点。

6. 发明授权

US08492233B2 Configurable NP channel lateral drain extended MOS-based transistor 有权
标题翻译：可配置NP沟道横向漏极扩展MOS晶体管
公开(公告)号：US08492233B2
公开(公告)日：2013-07-23
申请号：US12883726
申请日：2010-09-16
申请人： Marie Denison , Hannes Estl
发明人： Marie Denison , Hannes Estl
IPC分类号： H01L29/43
CPC分类号： H01L27/092 , H01L29/0634 , H01L29/0653 , H01L29/402 , H01L29/404 , H01L29/407 , H01L29/7816 , H01L29/7824 , H01L29/7831 , H01L29/7834 , H01L29/7835 , H01L29/7846
摘要： An integrated circuit containing a configurable dual n/p-channel 3-D resurf high voltage MOS field effect transistor (MOSFET) is disclosed. An n-channel drain is coterminous with a p-channel source in an n-well, and a p-channel drain is coterminous with an n-channel source in a p-well. A lateral drift region including n-type drift lanes and p-type drift lanes extends between the n and p wells. A resurf layer abuts the lateral drift region. The n-channel MOS gate is separate from the p-channel MOS gate. The p-channel MOS gate may be operated as a field plate in the n-channel mode, and vice versa. An n-channel MOS transistor may be integrated into the n-channel MOS source to provide an n-channel cascode transistor configuration, and similarly for a p-channel cascode configuration, to debias parasitic bipolar transistors under the MOS gates. Circuits using the MOSFET with various loads are also disclosed.
摘要翻译：公开了一种包含可配置的双n / p沟道3-D复用高压MOS场效应晶体管（MOSFET）的集成电路。 n沟道漏极在n阱中与p沟道源相邻，并且p沟道漏极与p阱中的n沟道源相邻。包括n型漂移通道和p型漂移通道的横向漂移区域在n阱和p阱之间延伸。再生层邻接横向漂移区域。 n沟道MOS栅极与p沟道MOS栅极分离。 p沟道MOS栅极可以作为n沟道模式中的场板操作，反之亦然。 n沟道MOS晶体管可以被集成到n沟道MOS源中以提供n沟道共源共栅晶体管配置，并且类似地用于p沟道共源共栅配置，以在MOS栅极之下去除寄生双极晶体管。还公开了使用具有各种负载的MOSFET的电路。

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