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1. 发明授权

US06788235B1 A/D converter having signaling and requesting capability 有权
标题翻译： A / D转换器具有信令和请求能力
公开(公告)号：US06788235B1
公开(公告)日：2004-09-07
申请号：US09581590
申请日：2000-07-26
申请人： Jens Barrenscheen , Gunther Fenzl , Peter Rohm , Dietmar Koenig , Dirk Elkemeier
发明人： Jens Barrenscheen , Gunther Fenzl , Peter Rohm , Dietmar Koenig , Dirk Elkemeier
IPC分类号： H03M112
CPC分类号： H03M1/12 , G06F3/05
摘要： The disclosed A/D conversion system is designed to signal the beginning or the impending beginning of an A/D conversion and/or to request the implementation of an A/D conversion from another A/D converter. As a result, it is possible to have a plurality of A/D converters work absolutely time-synchronously with minimal outlay.
摘要翻译：所公开的A / D转换系统被设计为用信号通知A / D转换的开始或即将开始和/或要求从另一个A / D转换器实现A / D转换。结果，可以使多个A / D转换器以最小的花费绝对时间同步工作。

2. 发明授权

US6147635A Timer for A/D converter 有权
标题翻译： A / D转换器定时器
公开(公告)号：US6147635A
公开(公告)日：2000-11-14
申请号：US307999
申请日：1999-05-10
申请人： Jens Barrenscheen , Peter Rohm , Gunther Fenzl
发明人： Jens Barrenscheen , Peter Rohm , Gunther Fenzl
IPC分类号： G06F3/05 , H03M1/12
CPC分类号： H03M1/1225
摘要： A timer for an A/D converter generates a request signal for A/D conversion by the A/D converter. In addition to the usual request signal, the timer produces a further signal which is used, before one cycle of the timer has elapsed, to block the A/D converter for low-priority requests from other requesting devices and to reserve it for the timer. In this manner, the signal to be converted from the timer can be sampled at reproducible, equidistant instants without having to wait for the end of the last conversion.
摘要翻译：用于A / D转换器的定时器通过A / D转换器产生用于A / D转换的请求信号。除了通常的请求信号之外，定时器还产生另一个信号，该信号在定时器的一个周期过去之前被使用，以阻止来自其他请求设备的低优先级请求的A / D转换器，并将其保留给定时器。以这种方式，从定时器转换的信号可以在可再现的等距时刻进行采样，而不必等待最后一次转换的结束。

3. 发明授权

US07350015B2 Data transmission device 有权
标题翻译：数据传输设备
公开(公告)号：US07350015B2
公开(公告)日：2008-03-25
申请号：US10285046
申请日：2002-10-31
申请人： Jens Barrenscheen , Gunther Fenzl , Peter Rohm
发明人： Jens Barrenscheen , Gunther Fenzl , Peter Rohm
IPC分类号： G06F13/36
CPC分类号： G06F13/28 , G06F13/4027
摘要： A data transmission device forwards data that have been received from a first device, intended for a second device, to the second device. The data transmission device is distinguished in that it has connections for connecting at least two data buses and can output data received by a first data bus either onto the same data bus or onto another data bus immediately or later. Therefore, the data transmission device can be used selectively, alternately or simultaneously as a DMA controller and a bus bridge. It also has additional functions unrelated to DMA controllers and bus bridges.
摘要翻译：数据传输设备将已经从第一设备接收的用于第二设备的数据转发到第二设备。数据传输设备的区别在于它具有用于连接至少两个数据总线的连接，并且可以立即或稍后地将由第一数据总线接收的数据输出到同一数据总线上或另一数据总线上。因此，数据传输设备可以选择性地，交替地或同时地用作DMA控制器和总线桥。它还具有与DMA控制器和总线桥接无关的附加功能。

4. 发明授权

US07133979B2 Method of transferring data between a first device and a second device while manipulating at least one quantity in dependence on an address 有权
标题翻译：在第一设备和第二设备之间传送数据的方法，同时根据地址操纵至少一个数量
公开(公告)号：US07133979B2
公开(公告)日：2006-11-07
申请号：US10008113
申请日：2001-11-08
申请人： Jens Barrenscheen , Hans Sulzer , Gunther Fenzl
发明人： Jens Barrenscheen , Hans Sulzer , Gunther Fenzl
IPC分类号： G06F13/00
CPC分类号： G06F13/385
摘要： A method for transferring data between a first device and a second device is provided. In the method an address identifying the second device is output by the first device or an address generating device connected downstream thereof. An association between the address and the device addressed as a result, and/or the data that are to be transferred are manipulated, during the transfer, in dependence on the outputted address.
摘要翻译：提供了一种用于在第一设备和第二设备之间传送数据的方法。在该方法中，识别第二设备的地址由第一设备或其下游连接的地址生成设备输出。根据所输出的地址，在传送过程中，操作地址和作为结果寻址的设备和/或要传送的数据之间的关联。

5. 发明授权

US06292862B1 Bridge module 失效
标题翻译：桥模块
公开(公告)号：US06292862B1
公开(公告)日：2001-09-18
申请号：US09123825
申请日：1998-07-28
申请人： Jens Barrenscheen , Gunther Fenzl , Achim Vowe
发明人： Jens Barrenscheen , Gunther Fenzl , Achim Vowe
IPC分类号： G06F1300
CPC分类号： H04L49/9057 , H04L12/46 , H04L12/4625 , H04L49/90 , H04L2012/40215 , H04L2012/40273
摘要： The bridge module is connected between at least two bus systems and is suitable for serial data transfer of binary data from one of the bus systems to the other one of the bus systems. A single memory device is provided for buffer storage of the data during a data transfer. The data transfer, which is controlled exclusively by the data to be transmitted, is thus carried out in a simple manner and completely automatically, without the interposition of a processor unit. It is thereby possible very easily and thus also at an attractive cost to specify a module which is suitable for the data transfer between different bus systems.
摘要翻译：桥模块连接在至少两个总线系统之间，适用于从一个总线系统到另一个总线系统的二进制数据的串行数据传输。提供单个存储器件用于在数据传输期间缓冲存储数据。因此，仅由所传送的数据进行控制的数据传送就能以简单的方式完全自动进行，而不需要插入处理器单元。因此，可以非常容易地并且因此也以有吸引力的成本来指定适合于不同总线系统之间的数据传输的模块。

6. 发明授权

US06653963B1 Method and apparatus for the A/D conversion of analog signals and corresponding A/D converter arrangement 有权
标题翻译：用于模拟信号的A / D转换和相应的A / D转换器装置的方法和装置
公开(公告)号：US06653963B1
公开(公告)日：2003-11-25
申请号：US10048346
申请日：2002-06-07
申请人： Jens Barrenscheen , Dietmar Konig , Gunther Fenzl
发明人： Jens Barrenscheen , Dietmar Konig , Gunther Fenzl
IPC分类号： H03M112
CPC分类号： H03M1/1225
摘要： An A/D converter arrangement comprises an A/D converter (6) to which analog signals from a plurality of signal channels (2) can be fed for A/D conversion. With the help of an appropriate control means (8), converter parameters of the A/D converter (6) or even other operating parameters of the A/D converter arrangement, such as certain functions performed in response to an A/D conversion which has been carried out for example, are set in a channel-specific way as a function of the signal channel (2) which is to be converted at the time.
摘要翻译： A / D转换器装置包括A / D转换器（6），来自多个信号通道（2）的模拟信号可以被馈送到A / D转换器，用于A / D转换。借助于适当的控制装置（8），A / D转换器（6）的转换器参数或甚至A / D转换器装置的其它操作参数，例如响应于A / D转换执行的某些功能，已经被执行，例如被设置为以通道特定的方式作为当时要转换的信号通道（2）的函数。

7. 发明授权

US06507298B1 Method for selecting, prioritizing, and A/D conversion of analog signals, and A/D converter configuration that prioritizes and selects signals 有权
标题翻译：用于选择，优先排序和模拟信号的A / D转换的方法以及优先选择信号的A / D转换器配置
公开(公告)号：US06507298B1
公开(公告)日：2003-01-14
申请号：US09708280
申请日：2000-11-08
申请人： Jens Barrenscheen , Gunther Fenzl
发明人： Jens Barrenscheen , Gunther Fenzl
IPC分类号： H03M112
CPC分类号： G06F3/05
摘要： A method for A/D conversion of analog signals using an A/D converter, and to an appropriate A/D converter circuit. In order to process converter request signals from different converter request sources requesting analog signals for conversion, the invention proposes assigning definable, selectable priorities to the different converter request sources. If there is a request for A/D conversion from a converter request source, the system establishes which of the converter request sources requesting A/D conversion has the highest priority. An analog signal from this selected converter request source is then supplied to the A/D converter.
摘要翻译：一种使用A / D转换器和适当的A / D转换器电路对模拟信号进行A / D转换的方法。为了处理来自请求模拟信号进行转换的不同转换器请求源的转换器请求信号，本发明提出向不同转换器请求源分配可定义的可选优先级。如果存在来自转换器请求源的A / D转换的请求，则系统确定请求A / D转换的转换器请求源中的哪一个具有最高优先级。然后将来自该选择的转换器请求源的模拟信号提供给A / D转换器。

8. 发明授权

US06421770B1 Buffer memory configuration having a memory between a USB and a CPU 失效
标题翻译：具有在USB和CPU之间的存储器的缓冲存储器配置
公开(公告)号：US06421770B1
公开(公告)日：2002-07-16
申请号：US09120160
申请日：1998-07-21
申请人： Martin Huch , Jens Barrenscheen , Gunther Fenzl
发明人： Martin Huch , Jens Barrenscheen , Gunther Fenzl
IPC分类号： G06F1202
CPC分类号： G06F5/16 , G06F5/10
摘要： The buffer memory configuration has a memory disposed between a USB and a central processing unit. The memory can be mapped onto an address space which is exactly half as large as the memory itself. The first half of the memory defines a first memory page and the second half of the memory defines a second memory page, and each address in the address space is assigned exactly one memory location on each of the memory pages. A memory management unit generates a first significant bit which assigns in each case the two memory locations having the same address to the address space of the first memory page and to the address space of the second memory page. The buffer memory architecture enables the memory independently to manage the data to be transferred. The two memory pages serve to decouple the central processing unit CPU and the bus. Both memory pages are virtually visible to the user but only one of the memory pages can ever be addressed for data transfer. Consequently, overlapping of the writing cycles is avoided by arranging the transmitted data and the data to be read out in separate areas of the memory.
摘要翻译：缓冲存储器配置具有设置在USB和中央处理单元之间的存储器。存储器可以被映射到正好与存储器本身一半一样大的地址空间。存储器的前半部分定义第一存储器页面，并且存储器的第二半部分定义第二存储器页面，并且每个存储器页面上分配地址空间中的每个地址恰好一个存储器位置。存储器管理单元产生第一有效位，其在每种情况下将具有相同地址的两个存储器位置分配给第一存储器页的地址空间和第二存储器页的地址空间。缓冲存储器架构使内存独立地管理要传输的数据。两个存储器页面用于去耦中央处理单元CPU和总线。两个内存页面对用户实际上是可见的，但只有一个内存页面可以被寻址用于数据传输。因此，通过将发送的数据和要在存储器的不同区域中读出的数据进行布置来避免写入周期的重叠。

9. 发明授权

US07228264B2 Program-controlled unit 有权
标题翻译：程控单位
公开(公告)号：US07228264B2
公开(公告)日：2007-06-05
申请号：US10116171
申请日：2002-04-04
申请人： Jens Barrenscheen , Gunther Fenzl
发明人： Jens Barrenscheen , Gunther Fenzl
IPC分类号： G06F9/455
CPC分类号： G06F11/3648 , G06F11/261
摘要： A program-controlled unit includes a selection device which can determine whether the program-controlled unit is to be emulated by using a first emulation unit or by using a second emulation unit. As a result, it is possible to provide a mass production version of the program-controlled unit with an emulation unit having a reduced functional and/or performance scope. Therefore, an emulatable mass production version of the program-controlled unit can be made available which is only insignificantly more expensive, if at all, than a non-emulatable version.
摘要翻译：程序控制单元包括可以通过使用第一仿真单元或通过使用第二仿真单元来确定程序控制单元是否被仿真的选择装置。结果，可以提供具有减少的功能和/或性能范围的仿真单元的程序控制单元的批量生产版本。因此，可以提供程序控制单元的可生产的批量生产版本，而不是不可升级的版本，这个版本只是不重要的昂贵。

10. 发明授权

US06912566B1 Memory device and method for operating the memory device 失效
标题翻译：用于操作存储器件的存储器件和方法
公开(公告)号：US06912566B1
公开(公告)日：2005-06-28
申请号：US09124288
申请日：1998-07-28
申请人： Jens Barrenscheen , Gunther Fenzl
发明人： Jens Barrenscheen , Gunther Fenzl
IPC分类号： H04L12/40 , G06F5/06 , G06F15/167
CPC分类号： G06F5/065
摘要： The memory device, for the purpose of serial data transfer of binary data, is arranged between at least two subscribers of a data transmission system. The memory is divided into a multiplicity of memory objects, which are typically of the same size and some of which are organized to form FIFO structures. The FIFO structures are used to buffer the typically asynchronous access operations between the subscribers at different data transmission rates and with a certain data depth, and to thereby decouple them from one another. The data transfer is largely under data control and thus requires minimal computation complexity in a central processing unit. The memory objects of the memory can advantageously be operated flexibly and independently of one another, in four different operating modes.
摘要翻译：用于二进制数据的串行数据传输的存储器件被布置在数据传输系统的至少两个用户之间。存储器被分成多个存储器对象，其通常具有相同的大小，并且其中一些被组织以形成FIFO结构。 FIFO结构用于以不同的数据传输速率和一定的数据深度来缓冲用户之间的异常访问操作，从而使它们彼此分离。数据传输主要在数据控制之下，因此在中央处理单元中需要最小的计算复杂度。在四种不同的操作模式中，存储器的存储器对象可以有利地彼此灵活地并且彼此独立地操作。

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