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1. 发明授权

US4478679A Self-aligning process for placing a barrier metal over the source and drain regions of MOS semiconductors 失效
标题翻译：用于在MOS半导体的源极和漏极区域上放置阻挡金属的自对准工艺
公开(公告)号：US4478679A
公开(公告)日：1984-10-23
申请号：US556722
申请日：1983-11-30
申请人： Jenq-Sian Chang , Yih-Jau Chang
发明人： Jenq-Sian Chang , Yih-Jau Chang
IPC分类号： H01L21/336 , H01L21/768 , H01L29/417 , C23F1/02 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L29/66575 , H01L21/7684 , H01L21/76895 , H01L29/41775 , H01L29/41783
摘要： A self-aligning process for adding a barrier metal to the source and drain regions of metal oxide semiconductors is presented. An oxide sidewall spacer is first formed on the sides of upwardly protruding gate regions. A barrier metal is then added to the entire surface, followed by adding a layer of resist material. The resist material is added in layers with each layer spun until the top surface is nearly smooth. An anisotropical etch is done to remove the resist everywhere except over the source and drain regions, which regions are depressed due to the upwardly protruding gate region and a surrounding upwardly protruding insulating material. The exposed barrier metal is etched away and the remaining resist is stripped, leaving a layer of barrier metal only over the source and drain regions.
摘要翻译：提出了一种用于向金属氧化物半导体的源极和漏极区域添加阻挡金属的自对准工艺。首先在向上突出的栅极区域的侧面上形成氧化物侧壁间隔物。然后将阻挡金属加入整个表面，然后加入一层抗蚀剂材料。将抗蚀剂材料分层加入，每层纺丝直到顶表面几乎平滑。进行各向异性蚀刻以去除除源极和漏极区域之外的所有其它抗蚀剂，该区域由于向上突出的栅极区域和周围的向上突出的绝缘材料而被压下。将暴露的阻挡金属蚀刻掉，剩余的抗蚀剂被剥离，仅在源极和漏极区域上留下一层阻挡金属。

2. 发明授权

US06255809B1 Method for measuring capacitance of passive device region 有权
标题翻译：无源器件区域电容测量方法
公开(公告)号：US06255809B1
公开(公告)日：2001-07-03
申请号：US09327895
申请日：1999-06-08
申请人： Sheng-Hsing Yang , Yih-Jau Chang
发明人： Sheng-Hsing Yang , Yih-Jau Chang
IPC分类号： G01R2726
CPC分类号： G01R27/2605 , H01L22/14
摘要： A method for measuring a capacitance of a passive device region. The passive device region is formed on a substrate having a conductive type different from that of the passive device region. Two bias voltages are applied to two terminals of the passive device region. By measuring the distance between these two terminals and the width of the passive device region, plus the grading coefficients of both area effect and sidewall effect, capacitance induced at both terminals can be derived.
摘要翻译：一种用于测量无源器件区域的电容的方法。无源器件区域形成在具有不同于无源器件区域的导电类型的衬底上。两个偏置电压施加到无源器件区域的两个端子。通过测量这两个端子之间的距离和无源器件区域的宽度，加上面积效应和侧壁效应的分级系数，可以推导出两端引起的电容。

3. 发明授权

US6040222A Method for fabricating an electrostatistic discharge protection device to protect an integrated circuit 失效
标题翻译：制造用于保护集成电路的静电放电保护装置的方法
公开(公告)号：US6040222A
公开(公告)日：2000-03-21
申请号：US241950
申请日：1999-02-02
申请人： Chen-Chung Hsu , Yih-Jau Chang
发明人： Chen-Chung Hsu , Yih-Jau Chang
IPC分类号： H01L21/336 , H01L21/8234 , H01L27/02
CPC分类号： H01L29/66492 , H01L21/823418 , H01L21/823443 , H01L21/823468 , H01L27/0266
摘要： An improved method for fabricating an ESD protection device so as to avoid ESD damage to a wafer. The improved method includes simultaneously forming an internal circuit and the ESD protection device without additional photomask or other process. The improved method uses a P.sup.+ doped region to take the place of an N.sup.- doped region of an interchangeable source/drain region with a LDD structure for the ESD protection device, of which its trigger voltage is adjusted by simply varying the P.sup.+ concentration.
摘要翻译：一种用于制造ESD保护装置以改善对晶片的ESD损伤的改进方法。改进的方法包括同时形成内部电路和ESD保护装置，而不需要额外的光掩模或其他工艺。改进的方法使用P +掺杂区域代替具有用于ESD保护器件的LDD结构的可互换源极/漏极区域的N-掺杂区域，其触发电压通过简单地改变P +浓度来调节。

4. 发明授权

US08252652B2 Semiconductor structure and fabrication method thereof 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08252652B2
公开(公告)日：2012-08-28
申请号：US12748703
申请日：2010-03-29
申请人： Yih-Jau Chang , Shang-Hui Tu , Gene Sheu , Yi-Fong Chang , Nithin Devarajulu Palavalli
发明人： Yih-Jau Chang , Shang-Hui Tu , Gene Sheu , Yi-Fong Chang , Nithin Devarajulu Palavalli
IPC分类号： H01L21/336 , H01L29/06
CPC分类号： H01L29/7835 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659
摘要： A semiconductor structure is provided. A second conductivity type well region is formed on a first conductivity type substrate. A second conductivity type diffused source and second conductivity type diffused drain are formed on the first conductivity type substrate. A gate structure is formed on the second conductivity type well region between the second conductivity type diffused source and the second conductivity type diffused drain. First conductivity type buried rings are arranged in a horizontal direction, and formed in the second conductivity type well region, and divide the second conductivity type well region into an upper drift region and a lower drift region.
摘要翻译：提供半导体结构。在第一导电型基板上形成第二导电类型阱区。在第一导电型基板上形成第二导电型扩散源极和第二导电型扩散漏极。在第二导电型扩散源和第二导电型扩散漏极之间的第二导电类型阱区上形成栅极结构。第一导电型掩埋环沿水平方向布置，并形成在第二导电类型阱区中，并将第二导电类型阱区划分为上漂移区和下漂移区。

5. 发明授权

US06319850B1 Method of forming dielectric layer with low dielectric constant 失效
标题翻译：形成低介电常数介电层的方法
公开(公告)号：US06319850B1
公开(公告)日：2001-11-20
申请号：US09294541
申请日：1999-04-19
申请人： Yih-Jau Chang , Chen-Chung Hsu
发明人： Yih-Jau Chang , Chen-Chung Hsu
IPC分类号： H01L2131
CPC分类号： H01L21/02131 , H01L21/02203 , H01L21/02304 , H01L21/02321 , H01L21/02337 , H01L21/02351 , H01L21/02362 , H01L21/31695
摘要： A method for forming a dielectric layer with a low dielectric constant (low-k) is described. A semiconductor substrate is provided. A dielectric layer is formed on the substrate. A doping step is performed on the dielectric layer. An annealing step is performed and a gas is simultaneously fed so that the dielectric layer is converted into the low-k dielectric layer.
摘要翻译：描述了形成具有低介电常数（低-k）的电介质层的方法。提供半导体衬底。在基板上形成电介质层。在电介质层上进行掺杂步骤。进行退火步骤，同时进料气体，使得电介质层转化为低k电介质层。

6. 发明授权

US6150261A Method of fabricating semiconductor device for preventing antenna effect 有权
标题翻译：制造防止天线效应的半导体器件的方法
公开(公告)号：US6150261A
公开(公告)日：2000-11-21
申请号：US318235
申请日：1999-05-25
申请人： Chen-Chung Hsu , Yih-Jau Chang
发明人： Chen-Chung Hsu , Yih-Jau Chang
IPC分类号： H01L21/768 , H01L23/485 , H01L21/4763
CPC分类号： H01L24/02 , H01L21/76892 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/04941 , H01L2924/13091
摘要： A method of fabricating a semiconductor device for preventing an antenna effect. In the invention, there is no additional mask layer or specific process performed. Thus, the fabrication cost does not increase. In addition, extra electrons are released through a path formed in the invention during the plasma-etching step. An antenna effect thus does not occur. The reliability of the semiconductor device is increased.
摘要翻译：一种制造用于防止天线效应的半导体器件的方法。在本发明中，没有附加的掩模层或特定的处理。因此，制造成本不增加。此外，在等离子蚀刻步骤期间，通过本发明中形成的路径释放额外的电子。因此不会发生天线效应。半导体器件的可靠性提高。

7. 发明授权

US5670397A Dual poly-gate deep submicron CMOS with buried contact technology 失效
标题翻译：双层多晶硅深亚微米CMOS埋层接触技术
公开(公告)号：US5670397A
公开(公告)日：1997-09-23
申请号：US783754
申请日：1997-01-16
申请人： Yih-Jau Chang , Shye-Lin Wu
发明人： Yih-Jau Chang , Shye-Lin Wu
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A CMOS device with buried contacts is formed using a polysilicon stack layer and twin-well and liquid phase deposition (LPD) processes. A gate oxide layer and a first polysilicon layer are formed on a substrate. Then the gate oxide and first polysilicon layer are etched to form gate structures. A polysilicon stack layer is formed on the gate structures. The polysilicon stack layer and the first polysilicon layer are anisotropically dry etched, forming first trenches that expose portions of the gate oxide and portions of the substrate defining S/D regions for a NMOSFET. A NMOS lightly doped drain (LDD) with halo doping profile is implanted. A first LPD oxide is selectively formed in the first trenches. Subsequently, a first heavy ion implantation is performed into the polysilicon stack layer for forming the source, drain, gate and buried contacts of the NMOSFET. Trenches are formed in the polysilicon stack layer and first polysilicon layer to define S/D regions and buried contacts for a PMOSFET. A PMOS LDD with halo doping profile is implanted. A second LPD oxide is selectively formed in the second trenches. A second heavy ion implantation is performed into the polysilicon stack layer to form the source, drain, gate and buried contacts of the PMOSFET. A thermal treatment is used to condense the LPD oxide and to activate the S/D implants and diffuse the heavy implants from the polysilicon stack layer into the substrate to form the buried contacts.
摘要翻译：具有埋入触点的CMOS器件使用多晶硅堆叠层和双阱和液相沉积（LPD）工艺形成。在基板上形成栅极氧化层和第一多晶硅层。然后蚀刻栅极氧化物和第一多晶硅层以形成栅极结构。在栅极结构上形成多晶硅堆叠层。多晶硅堆叠层和第一多晶硅层被各向异性地干蚀刻，形成第一沟槽，其暴露出栅极氧化物的部分和限定用于NMOSFET的S / D区域的衬底的部分。注入具有晕圈掺杂分布的NMOS轻掺杂漏极（LDD）。在第一沟槽中选择性地形成第一LPD氧化物。随后，对多晶硅叠层进行第一次重离子注入，以形成NMOSFET的源极，漏极，栅极和埋入触点。沟槽形成在多晶硅堆叠层和第一多晶硅层中以限定用于PMOSFET的S / D区域和埋入触点。植入具有晕圈掺杂分布的PMOS LDD。在第二沟槽中选择性地形成第二LPD氧化物。对多晶硅堆叠层进行第二次重离子注入以形成PMOSFET的源极，漏极，栅极和埋入触点。热处理用于冷凝LPD氧化物并激活S / D植入物，并将重掺杂物从多晶硅堆叠层扩散到衬底中以形成掩埋触点。

8. 发明授权

US08154078B2 Semiconductor structure and fabrication method thereof 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08154078B2
公开(公告)日：2012-04-10
申请号：US12707419
申请日：2010-02-17
申请人： Yih-Jau Chang , Shang-Hui Tu , Gene Sheu
发明人： Yih-Jau Chang , Shang-Hui Tu , Gene Sheu
IPC分类号： H01L29/66
CPC分类号： H01L29/7835 , H01L29/0634 , H01L29/0696 , H01L29/42368 , H01L29/66659
摘要： A semiconductor structure is provided. A second conductivity type well region is disposed on a first conductivity type substrate. A gate structure comprising a first sidewall and second sidewall is provided. The first sidewall is disposed on the second conductivity type well region. A second conductivity type diffused source is disposed on the first conductivity type substrate outside of the second sidewall. A second conductivity type diffused drain is disposed on the second conductivity type well region outside of the first sidewall. First conductivity type buried rings are arranged in a horizontal direction, separated from each other, and formed in the second conductivity type well region. Doped profiles of the first conductivity type buried rings gradually become smaller in a direction from the second conductivity type diffused source to the second conductivity type diffused drain.
摘要翻译：提供半导体结构。第二导电类型阱区设置在第一导电类型的衬底上。提供包括第一侧壁和第二侧壁的栅极结构。第一侧壁设置在第二导电类型的井区上。第二导电型扩散源设置在第二侧壁外侧的第一导电型基板上。第二导电类型扩散漏极设置在第一侧壁外侧的第二导电类型阱区上。第一导电型掩埋环布置在水平方向上，彼此分离，并形成在第二导电类型阱区中。第一导电型掩埋环的掺杂分布在从第二导电型扩散源到第二导电型扩散漏极的方向上逐渐变小。

9. 发明授权

US06274494B1 Method of protecting gate oxide 失效
标题翻译：保护栅极氧化物的方法
公开(公告)号：US06274494B1
公开(公告)日：2001-08-14
申请号：US09215632
申请日：1998-12-16
申请人： Mu-Chun Wang , Yih-Jau Chang
发明人： Mu-Chun Wang , Yih-Jau Chang
IPC分类号： H01L2144
CPC分类号： H01L21/76841 , H01L21/28176
摘要： A method of protecting gate oxide. A chip having a gate thereon is provided. The gate structure comprises a gate oxide layer and a gate electrode. The gate is covered by a dielectric layer. A protection layer is formed on the dielectric layer. The protection layer is pattern to remain a part of the protection layer aligned over the gate.
摘要翻译：保护栅极氧化物的方法。提供了具有栅极的芯片。栅极结构包括栅极氧化物层和栅电极。栅极被介电层覆盖。在电介质层上形成保护层。保护层的图案是保持在栅极上对准的保护层的一部分。

10. 发明授权

US06225166B1 Method of manufacturing electrostatic discharge protective circuit 有权
标题翻译：制造静电放电保护电路的方法
公开(公告)号：US06225166B1
公开(公告)日：2001-05-01
申请号：US09304223
申请日：1999-05-03
申请人： Chen-Chung Hsu , Yih-Jau Chang
发明人： Chen-Chung Hsu , Yih-Jau Chang
IPC分类号： H01L218234
CPC分类号： H01L27/0266 , H01L21/28518 , H01L21/823418 , H01L21/823443
摘要： A method of manufacturing an electrostatic discharge protective circuit. A substrate having an inner circuit region and an electrostatic discharge protective circuit is provided. The inner circuit region comprises a first gate electrode, a source/drain region and a first suicide layer formed on the first gate electrode. The electrostatic discharge protective circuit region comprises a second gate electrode and a second silicide layer formed on the second gate electrode. A salicide block layer is formed to cover the electrostatic discharge protective circuit region. A salicide process is performed. The salicide block layer is removed to expose the electrostatic discharge protective circuit region.
摘要翻译：一种制造静电放电保护电路的方法。提供具有内部电路区域和静电放电保护电路的衬底。内部电路区域包括第一栅极电极，源极/漏极区域和形成在第一栅极电极上的第一硅化物层。静电放电保护电路区域包括形成在第二栅电极上的第二栅电极和第二硅化物层。形成一个覆盖静电放电保护电路区域的自对准硅化物阻挡层。执行自杀化合物处理。去除自对准硅化物阻挡层以暴露静电放电保护电路区域。

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