会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 5. 发明申请
    • DISTRESS SIGNAL TRANSMITTERS
    • DISTRESS信号发射器
    • US20170069195A1
    • 2017-03-09
    • US14840027
    • 2015-08-30
    • David Yen ShauJeng-Jye Shau
    • David Yen ShauJeng-Jye Shau
    • G08B21/08
    • G08B21/088G01S5/0231
    • Distress signal transmitters of the present invention are designed to maximize the chance for a victim to survive an accident, and minimize the time for a rescue party to find a victim. The preferred embodiments of the distress signal transmitters of the present invention are to be self-powered, self-activated, and to remain fully functional when dropped into salt water. This will allow the Radio Frequency (RF) distress signals to be sent over a long distance, even if the user is unconscious or severely injured. Furthermore, a set of coordinates determined by a Global Positioning System will be transmitted with the S.O.S message in order for search parties to quickly and efficiently pinpoint the location of the victim(s).
    • 本发明的遇险信号发射器被设计成使得受害者在事故中生存的机会最大化,并且使救援人员找到受害者的时间最小化。 本发明的遇险信号发射机的优选实施例将是自供电的,自激活的,并且在落入盐水时保持完全功能。 即使使用者无意识或严重受伤,这样也可以使射频(RF)遇险信号长距离发送。 此外,由全球定位系统确定的一组坐标将与S.O.S消息一起发送,以便搜索方快速有效地确定受害者的位置。
    • 10. 发明申请
    • Capacitor coupling circuits
    • 电容耦合电路
    • US20050201025A1
    • 2005-09-15
    • US10796318
    • 2004-03-09
    • Jeng-Jye Shau
    • Jeng-Jye Shau
    • H02H7/00
    • H01L29/94H01L27/0629H01L27/0688H01L27/11524H01L27/11551H01L27/118H01L28/60H01L29/788H03K19/018521H03K19/0941
    • The present invention utilizes voltage coupling effects of MOS capacitors to support logic operations for integrated circuits such as programmable logic array, optical sensors, comparators, and storage devices. Additional flexibility is achieved by using the voltage coupling effects of floating gate capacitors to support applications such as field programmable logic and non-volatile memory devices. Integrated circuits of the present invention occupy much smaller areas comparing to equivalent prior art integrated circuits, achieving dramatic cost reduction. Further cost reduction can be achieved by fabricating coupling circuits of the present invention on low quality substrates as 3 dimensional devices. The major drawback of the present invention is smaller signal to noise ratio, which is overcome by proper voltage control and sensing circuits. Special considerations to support hot carrier programming and current mode reading are also disclosed in this patent.
    • 本发明利用MOS电容器的电压耦合效应来支持诸如可编程逻辑阵列,光学传感器,比较器和存储装置之类的集成电路的逻辑运算。 通过使用浮动栅极电容器的电压耦合效应来支持诸如现场可编程逻辑和非易失性存储器件的应用来实现额外的灵活性。 与现有技术的集成电路相比,本发明的集成电路占据了更小的面积,从而实现了显着的成本降低。 通过将本发明的耦合电路制成低质量的基板作为3维器件,可以进一步降低成本。 本发明的主要缺陷是较小的信噪比,这被适当的电压控制和感测电路所克服。 本专利还公开了支持热载波编程和当前模式读取的特殊考虑。