专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08456915B2 Programming non-volatile storage with fast bit detection and verify skip 有权
标题翻译：使用快速位检测编程非易失性存储并进行验证跳过
公开(公告)号：US08456915B2
公开(公告)日：2013-06-04
申请号：US13436805
申请日：2012-03-30
申请人： Changyuan Chen , Jeffrey Lutze , Yingda Dong , Hua-Ling Hsu
发明人： Changyuan Chen , Jeffrey Lutze , Yingda Dong , Hua-Ling Hsu
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G10L15/26 , G11C2211/5621
摘要： A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.
摘要翻译：对一组非易失性存储元件进行编程处理以便存储数据。在编程过程中，执行一个或多个验证操作以确定非易失性存储元件是否已经达到其目标。对被编程到一个或多个目标的第一组的非易失性存储元件进行验证以确定它们是否已经达到其目标，并且如果确定它们已经达到其目标，则被锁定进一步编程。被编程到一个或多个目标的第二组的非易失性存储元件被测试以确定快速编程位的数量。当特定目标的快速位数大于阈值时，则对于被编程到特定目标的非易失性存储元件的编程停止。

2. 发明授权

US08406053B1 On chip dynamic read for non-volatile storage 有权
标题翻译：用于非易失性存储的片上动态读取
公开(公告)号：US08406053B1
公开(公告)日：2013-03-26
申请号：US13239194
申请日：2011-09-21
申请人： Deepanshu Dutta , Dana Lee , Jeffrey Lutze
发明人： Deepanshu Dutta , Dana Lee , Jeffrey Lutze
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/04 , G11C11/5642 , G11C16/26 , G11C16/3418 , G11C16/3495 , G11C2211/5644
摘要： Dynamically determining read levels on chip (e.g., memory die) is disclosed herein. One method comprises reading a group of non-volatile storage elements on a memory die at a first set of read levels. Results of the two most recent of the read levels are stored on the memory die. A count of how many of the non-volatile storage elements in the group showed a different result between the reads for the two most recent read levels is determined. The determining is performed on the memory die using the results stored on the memory die. A dynamic read level is determined for distinguishing between a first pair of adjacent data states of the plurality of data states based on the read level when the count reaches a pre-determined criterion. Note that the read level may be dynamically determined on the memory die.
摘要翻译：本文公开了动态地确定芯片上的读取电平（例如，存储器管芯）。一种方法包括以第一组读取级别在存储器管芯上读取一组非易失性存储元件。两个最新的读取电平的结果存储在存储器管芯上。确定组中有多少非易失性存储元件在两个最新读取级别的读取之间显示不同的结果。使用存储在存储器管芯上的结果在存储器管芯上进行确定。当计数达到预定标准时，基于读取级别来确定动态读取级别以区分多个数据状态的第一对相邻数据状态。注意，读取电平可以在存储器管芯上动态地确定。

3. 发明申请

US20120188824A1 PROGRAMMING NON-VOLATILE STORAGE WITH FAST BIT DETECTION AND VERIFY SKIP 有权
标题翻译：使用快速检测和验证跳过编程非易失性存储
公开(公告)号：US20120188824A1
公开(公告)日：2012-07-26
申请号：US13436805
申请日：2012-03-30
申请人： Changyuan Chen , Jeffrey Lutze , Yingda Dong , Hua-Ling Hsu
发明人： Changyuan Chen , Jeffrey Lutze , Yingda Dong , Hua-Ling Hsu
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C11/5628 , G10L15/26 , G11C2211/5621
摘要： A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.
摘要翻译：对一组非易失性存储元件进行编程处理以便存储数据。在编程过程中，执行一个或多个验证操作以确定非易失性存储元件是否已经达到其目标。对被编程到一个或多个目标的第一组的非易失性存储元件进行验证以确定它们是否已经达到其目标，并且如果确定它们已经达到其目标，则被锁定进一步编程。被编程到一个或多个目标的第二组的非易失性存储元件被测试以确定快速编程位的数量。当特定目标的快速位数大于阈值时，则对于被编程到特定目标的非易失性存储元件的编程停止。

4. 发明授权

US08174895B2 Programming non-volatile storage with fast bit detection and verify skip 有权
标题翻译：使用快速位检测编程非易失性存储并进行验证跳过
公开(公告)号：US08174895B2
公开(公告)日：2012-05-08
申请号：US12638853
申请日：2009-12-15
申请人： Changyuan Chen , Jeffrey Lutze , Yingda Dong , Hua-Ling Hsu
发明人： Changyuan Chen , Jeffrey Lutze , Yingda Dong , Hua-Ling Hsu
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G10L15/26 , G11C2211/5621
摘要： A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.
摘要翻译：对一组非易失性存储元件进行编程处理以便存储数据。在编程过程中，执行一个或多个验证操作以确定非易失性存储元件是否已经达到其目标。对被编程到一个或多个目标的第一组的非易失性存储元件进行验证以确定它们是否已经达到其目标，并且如果确定它们已经达到其目标，则被锁定进一步编程。被编程到一个或多个目标的第二组的非易失性存储元件被测试以确定快速编程位的数量。当特定目标的快速位数大于阈值时，则对于被编程到特定目标的非易失性存储元件的编程停止。

5. 发明授权

US08111554B2 Starting program voltage shift with cycling of non-volatile memory 有权
标题翻译：通过非易失性存储器循环启动程序电压漂移
公开(公告)号：US08111554B2
公开(公告)日：2012-02-07
申请号：US12572069
申请日：2009-10-01
申请人： Jeffrey Lutze
发明人： Jeffrey Lutze
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/0483
摘要： A system is disclosed for programming non-volatile storage that improves performance by setting the starting programming voltage to a first level for fresh parts and adjusting the starting programming voltage as the memory is cycled. For example, the system programs a set of non-volatile storage elements during a first period using an increasing program signal with a first initial value and subsequently programs the set of non-volatile storage elements during a second period using an increasing program signal with a second initial value, where the second period is subsequent to the first period and the second initial value is different than the first initial value.
摘要翻译：公开了一种用于编程非易失性存储器的系统，其通过将起始编程电压设置为新鲜部件的第一电平并在存储器循环时调整起始编程电压来提高性能。例如，该系统使用具有第一初始值的增加的程序信号在第一时段期间对一组非易失性存储元件进行编程，并且随后使用增加的程序信号在第二周期期间对该组非易失性存储元件进行编程，第二初始值，其中第二周期在第一周期之后且第二初始值不同于第一初始值。

6. 发明授权

US07623389B2 System for low voltage programming of non-volatile memory cells 有权
标题翻译：非易失性存储单元低压编程系统
公开(公告)号：US07623389B2
公开(公告)日：2009-11-24
申请号：US11614884
申请日：2006-12-21
申请人： Dana Lee , Jeffrey Lutze
发明人： Dana Lee , Jeffrey Lutze
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/10
摘要： System for programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline by injecting hot carriers from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n−1) into a floating gate of the selected non-volatile memory cell on the wordline WL(n).
摘要翻译：用于通过从注入存储器单元的漏极区域注入热载流子来对存储器阵列中的所选择的非易失性存储单元进行编程的系统，所述存储器阵列具有耦合到字线WL（n）的栅极节点和连接到所选位线的漏极节点门节点与下一个相邻字线WL（n-1）耦合到字线WL（n）上的所选择的非易失性存储器单元的浮动栅极。

7. 发明授权

US07447065B2 Reducing read disturb for non-volatile storage 有权
公开(公告)号：US07447065B2
公开(公告)日：2008-11-04
申请号：US12021741
申请日：2008-01-29
申请人： Yupin Fong , Jun Wan , Jeffrey Lutze
发明人： Yupin Fong , Jun Wan , Jeffrey Lutze
IPC分类号： G11C11/34
CPC分类号： G11C16/3418 , G11C16/3427
摘要： A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.

8. 发明申请

US20080084761A1 HYBRID PROGRAMMING METHODS AND SYSTEMS FOR NON-VOLATILE MEMORY STORAGE ELEMENTS 有权
标题翻译：非易失性存储元件的混合编程方法和系统
公开(公告)号：US20080084761A1
公开(公告)日：2008-04-10
申请号：US11535452
申请日：2006-09-26
申请人： Dana Lee , Yingda Dong , Changyuan Chen , Jeffrey Lutze
发明人： Dana Lee , Yingda Dong , Changyuan Chen , Jeffrey Lutze
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： A hybrid method of programming a non-volatile memory cell to a final programmed state is described. The method described is a more robust protocol suitable for reliably programming selected memory cells while eliminating programming disturbs. The hybrid method comprises programming the non-volatile memory cell to a first state according to a first coarse programming mechanism, and programming the non-volatile memory cell according to a second different more precise programming mechanism thereby completing the programming of the non-volatile memory cell to the final programmed state. Additionally, the described method is particularly advantageous for programming multilevel chips.
摘要翻译：描述了将非易失性存储器单元编程到最终编程状态的混合方法。所描述的方法是一种更鲁棒的协议，适用于可靠地编程所选择的存储器单元，同时消除编程干扰。混合方法包括根据第一粗略编程机制将非易失性存储器单元编程为第一状态，以及根据第二种不同的更精确的编程机制对非易失性存储器单元进行编程，由此完成非易失性存储器的编程单元格到最终编程状态。另外，所描述的方法对于编程多级芯片是特别有利的。

9. 发明授权

US07262994B2 System for reducing read disturb for non-volatile storage 有权
公开(公告)号：US07262994B2
公开(公告)日：2007-08-28
申请号：US11296087
申请日：2005-12-06
申请人： Yupin Fong , Jun Wan , Jeffrey Lutze
发明人： Yupin Fong , Jun Wan , Jeffrey Lutze
IPC分类号： G11C11/34
CPC分类号： G11C16/3418 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3427
摘要： A system for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.

10. 发明申请

US20070147113A1 Alternate sensing techniques for non-volatile memories 有权
标题翻译：用于非易失性存储器的替代传感技术
公开(公告)号：US20070147113A1
公开(公告)日：2007-06-28
申请号：US11321996
申请日：2005-12-28
申请人： Nima Mokhlesi , Jeffrey Lutze
发明人： Nima Mokhlesi , Jeffrey Lutze
IPC分类号： G11C16/04 , G11C16/06 , G11C11/34
CPC分类号： G11C16/28
摘要： The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to charge up. The bit line of the memory cell will then charge up until the bit line voltage becomes sufficiently high to shut off any further cell conduction. The rise of the bit line voltage will occur at a rate and to a level dependent upon the data state of the cell, and the cell will then shut off when the bit line reaches a high enough level such that the body effect affected memory cell threshold is reached, at which point the current essentially shuts off. A particular embodiment performs multiple such sensing sub-operations, each with a different control gate voltage, but with multiple states being sensed in each operation by charging the previously discharged cells up through their source.
摘要翻译：本发明提供了一种用于感测存储器单元的方案。所选择的存储单元通过其通道放电到地，然后将电压电平放置在传统源上，并将另一个电压电平放置在控制栅上，并允许单元位线充电。存储单元的位线然后将充电直到位线电压变得足够高以截止任何进一步的单元导通。位线电压的升高将以一定的速率发生，并且取决于单元的数据状态，并且当位线达到足够高的电平时，单元将关闭，使得体效应影响存储单元阈值到达目前，当前基本上关闭。特定实施例执行多个这样的感测子操作，每个具有不同的控制栅极电压，但是在每个操作中通过对先前放电的单元通过其源极充电来感测多个状态。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式