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1. 发明申请

US20080151628A1 SYSTEM FOR LOW VOLTAGE PROGRAMMING OF NON-VOLATILE MEMORY CELLS 有权
标题翻译：非挥发性记忆体低电压编程系统
公开(公告)号：US20080151628A1
公开(公告)日：2008-06-26
申请号：US11614884
申请日：2006-12-21
申请人： Dana Lee , Jeffrey Lutze
发明人： Dana Lee , Jeffrey Lutze
IPC分类号： G11C16/10
CPC分类号： G11C16/0483 , G11C16/10
摘要： System for programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline by injecting hot carriers from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n−1) into a floating gate of the selected non-volatile memory cell on the wordline WL(n).
摘要翻译：用于通过从注入存储器单元的漏极区域注入热载流子来对存储器阵列中的所选择的非易失性存储单元进行编程的系统，所述存储器阵列具有耦合到字线WL（n）的栅极节点和连接到所选位线的漏极节点门节点与下一个相邻字线WL（n-1）耦合到字线WL（n）上的所选择的非易失性存储器单元的浮动栅极。

2. 发明授权

US08406053B1 On chip dynamic read for non-volatile storage 有权
标题翻译：用于非易失性存储的片上动态读取
公开(公告)号：US08406053B1
公开(公告)日：2013-03-26
申请号：US13239194
申请日：2011-09-21
申请人： Deepanshu Dutta , Dana Lee , Jeffrey Lutze
发明人： Deepanshu Dutta , Dana Lee , Jeffrey Lutze
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/04 , G11C11/5642 , G11C16/26 , G11C16/3418 , G11C16/3495 , G11C2211/5644
摘要： Dynamically determining read levels on chip (e.g., memory die) is disclosed herein. One method comprises reading a group of non-volatile storage elements on a memory die at a first set of read levels. Results of the two most recent of the read levels are stored on the memory die. A count of how many of the non-volatile storage elements in the group showed a different result between the reads for the two most recent read levels is determined. The determining is performed on the memory die using the results stored on the memory die. A dynamic read level is determined for distinguishing between a first pair of adjacent data states of the plurality of data states based on the read level when the count reaches a pre-determined criterion. Note that the read level may be dynamically determined on the memory die.
摘要翻译：本文公开了动态地确定芯片上的读取电平（例如，存储器管芯）。一种方法包括以第一组读取级别在存储器管芯上读取一组非易失性存储元件。两个最新的读取电平的结果存储在存储器管芯上。确定组中有多少非易失性存储元件在两个最新读取级别的读取之间显示不同的结果。使用存储在存储器管芯上的结果在存储器管芯上进行确定。当计数达到预定标准时，基于读取级别来确定动态读取级别以区分多个数据状态的第一对相邻数据状态。注意，读取电平可以在存储器管芯上动态地确定。

3. 发明授权

US07623389B2 System for low voltage programming of non-volatile memory cells 有权
标题翻译：非易失性存储单元低压编程系统
公开(公告)号：US07623389B2
公开(公告)日：2009-11-24
申请号：US11614884
申请日：2006-12-21
申请人： Dana Lee , Jeffrey Lutze
发明人： Dana Lee , Jeffrey Lutze
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/10
摘要： System for programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline by injecting hot carriers from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n−1) into a floating gate of the selected non-volatile memory cell on the wordline WL(n).
摘要翻译：用于通过从注入存储器单元的漏极区域注入热载流子来对存储器阵列中的所选择的非易失性存储单元进行编程的系统，所述存储器阵列具有耦合到字线WL（n）的栅极节点和连接到所选位线的漏极节点门节点与下一个相邻字线WL（n-1）耦合到字线WL（n）上的所选择的非易失性存储器单元的浮动栅极。

4. 发明申请

US20080084761A1 HYBRID PROGRAMMING METHODS AND SYSTEMS FOR NON-VOLATILE MEMORY STORAGE ELEMENTS 有权
标题翻译：非易失性存储元件的混合编程方法和系统
公开(公告)号：US20080084761A1
公开(公告)日：2008-04-10
申请号：US11535452
申请日：2006-09-26
申请人： Dana Lee , Yingda Dong , Changyuan Chen , Jeffrey Lutze
发明人： Dana Lee , Yingda Dong , Changyuan Chen , Jeffrey Lutze
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： A hybrid method of programming a non-volatile memory cell to a final programmed state is described. The method described is a more robust protocol suitable for reliably programming selected memory cells while eliminating programming disturbs. The hybrid method comprises programming the non-volatile memory cell to a first state according to a first coarse programming mechanism, and programming the non-volatile memory cell according to a second different more precise programming mechanism thereby completing the programming of the non-volatile memory cell to the final programmed state. Additionally, the described method is particularly advantageous for programming multilevel chips.
摘要翻译：描述了将非易失性存储器单元编程到最终编程状态的混合方法。所描述的方法是一种更鲁棒的协议，适用于可靠地编程所选择的存储器单元，同时消除编程干扰。混合方法包括根据第一粗略编程机制将非易失性存储器单元编程为第一状态，以及根据第二种不同的更精确的编程机制对非易失性存储器单元进行编程，由此完成非易失性存储器的编程单元格到最终编程状态。另外，所描述的方法对于编程多级芯片是特别有利的。

5. 发明授权

US07961511B2 Hybrid programming methods and systems for non-volatile memory storage elements 有权
标题翻译：用于非易失性存储器存储元件的混合编程方法和系统
公开(公告)号：US07961511B2
公开(公告)日：2011-06-14
申请号：US11535452
申请日：2006-09-26
申请人： Dana Lee , Yingda Dong , Changyuan Chen , Jeffrey Lutze
发明人： Dana Lee , Yingda Dong , Changyuan Chen , Jeffrey Lutze
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： A hybrid method of programming a non-volatile memory cell to a final programmed state is described. The method described is a more robust protocol suitable for reliably programming selected memory cells while eliminating programming disturbs. The hybrid method comprises programming the non-volatile memory cell to a first state according to a first coarse programming mechanism, and programming the non-volatile memory cell according to a second different more precise programming mechanism thereby completing the programming of the non-volatile memory cell to the final programmed state. Additionally, the described method is particularly advantageous for programming multilevel chips.
摘要翻译：描述了将非易失性存储器单元编程到最终编程状态的混合方法。所描述的方法是一种更鲁棒的协议，适用于可靠地编程所选择的存储器单元，同时消除编程干扰。混合方法包括根据第一粗略编程机制将非易失性存储器单元编程为第一状态，以及根据第二种不同的更精确的编程机制对非易失性存储器单元进行编程，由此完成非易失性存储器的编程单元格到最终编程状态。另外，所描述的方法对于编程多级芯片是特别有利的。

6. 发明申请

US20130070524A1 ON CHIP DYNAMIC READ FOR NON-VOLATILE STORAGE 有权
标题翻译：在芯片动态阅读非易失性存储
公开(公告)号：US20130070524A1
公开(公告)日：2013-03-21
申请号：US13239194
申请日：2011-09-21
申请人： Deepanshu Dutta , Dana Lee , Jeffrey Lutze
发明人： Deepanshu Dutta , Dana Lee , Jeffrey Lutze
IPC分类号： G11C16/10
CPC分类号： G11C16/04 , G11C11/5642 , G11C16/26 , G11C16/3418 , G11C16/3495 , G11C2211/5644
摘要： Dynamically determining read levels on chip (e.g., memory die) is disclosed herein. One method comprises reading a group of non-volatile storage elements on a memory die at a first set of read levels. Results of the two most recent of the read levels are stored on the memory die. A count of how many of the non-volatile storage elements in the group showed a different result between the reads for the two most recent read levels is determined. The determining is performed on the memory die using the results stored on the memory die. A dynamic read level is determined for distinguishing between a first pair of adjacent data states of the plurality of data states based on the read level when the count reaches a pre-determined criterion. Note that the read level may be dynamically determined on the memory die.
摘要翻译：本文公开了动态地确定芯片上的读取电平（例如，存储器管芯）。一种方法包括以第一组读取级别在存储器管芯上读取一组非易失性存储元件。两个最新的读取电平的结果存储在存储器管芯上。确定组中有多少非易失性存储元件在两个最新读取级别的读取之间显示不同的结果。使用存储在存储器管芯上的结果在存储器管芯上进行确定。当计数达到预定标准时，基于读取级别来确定动态读取级别以区分多个数据状态的第一对相邻数据状态。注意，读取电平可以在存储器管芯上动态地确定。

7. 发明授权

US07944749B2 Method of low voltage programming of non-volatile memory cells 有权
标题翻译：非易失性存储单元低压编程方法
公开(公告)号：US07944749B2
公开(公告)日：2011-05-17
申请号：US11614879
申请日：2006-12-21
申请人： Dana Lee , Jeffrey Lutze
发明人： Dana Lee , Jeffrey Lutze
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： A low voltage method of programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline by injecting hot carriers from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n−1) into a floating gate of the selected non-volatile memory cell on the wordline WL(n).
摘要翻译：一种低电压方法，通过从注入存储器的漏极区域注入热载流子来对存储器阵列中的所选择的非易失性存储单元进行编程，所述存储器阵列具有耦合到字线WL（n）的栅极节点和连接到选定位线的漏极节点小区具有耦合到下一个相邻字线WL（n-1）的门节点到位于字线WL（n）上的所选择的非易失性存储器单元的浮动栅极。

8. 发明申请

US20080151627A1 METHOD OF LOW VOLTAGE PROGRAMMING OF NON-VOLATILE MEMORY CELLS 有权
标题翻译：非挥发性记忆细胞低电压编程方法
公开(公告)号：US20080151627A1
公开(公告)日：2008-06-26
申请号：US11614879
申请日：2006-12-21
申请人： Dana Lee , Jeffrey Lutze
发明人： Dana Lee , Jeffrey Lutze
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： A low voltage method of programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline by injecting hot carriers from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n-1) into a floating gate of the selected non-volatile memory cell on the wordline WL(n).
摘要翻译：一种低电压方法，通过从注入存储器的漏极区域注入热载流子来对存储器阵列中的所选择的非易失性存储单元进行编程，所述存储器阵列具有耦合到字线WL（n）的栅极节点和连接到选定位线的漏极节点小区具有耦合到下一个相邻字线WL（n-1）的门节点到位于字线WL（n）上的所选择的非易失性存储器单元的浮动栅极。

9. 发明授权

US09430322B2 Device based wear leveling using intrinsic endurance 有权
标题翻译：基于设备的磨损均衡使用内在的耐力
公开(公告)号：US09430322B2
公开(公告)日：2016-08-30
申请号：US13565650
申请日：2012-08-02
申请人： Jonathan Wolfman , Dana Lee , Jonathan Hsu
发明人： Jonathan Wolfman , Dana Lee , Jonathan Hsu
IPC分类号： G06F12/02 , G06F11/10 , H04L1/00 , G06F11/30 , G01R31/317 , G06F12/06 , G11C16/04 , G06F11/07 , G06F12/16 , G11C16/34 , G11C29/04
CPC分类号： G06F11/1048 , G01R31/3171 , G06F11/07 , G06F11/076 , G06F11/30 , G06F12/02 , G06F12/0246 , G06F12/06 , G06F12/16 , G06F2212/7211 , G11C16/04 , G11C16/34 , G11C16/349 , G11C2029/0409 , H04L1/0061
摘要： A system for improving the management and usage of blocks based on intrinsic endurance may be used to improve memory usage for flash memory, such as a memory card. The overall card endurance may be extended by cycling blocks with higher intrinsic endurance over the lowest endurance target of the worst block. This may be accomplished by managing blocks with different intrinsic endurance values internally or by partitioning the blocks with different intrinsic endurance values externally for different usage.
摘要翻译：可以使用用于改善基于固有耐力的块的管理和使用的系统来改善诸如存储卡的闪存的存储器使用。整体卡耐力可以通过在最差块的最低耐力目标下具有较高内在耐力的循环块来延长。这可以通过内部管理具有不同内在耐力值的块来实现，或者通过外部对不同的内在耐力值进行分区，以实现不同的使用。

10. 发明授权

US09152497B2 Data recovery from blocks with gate shorts 有权
标题翻译：从具有门短路的块中恢复数据
公开(公告)号：US09152497B2
公开(公告)日：2015-10-06
申请号：US13974997
申请日：2013-08-23
申请人： Dana Lee , Abhijeet Manohar
发明人： Dana Lee , Abhijeet Manohar
IPC分类号： G11C29/00 , G06F11/10 , G11C16/34 , G11C29/50 , G11C29/04
CPC分类号： G06F11/1068 , G06F11/1048 , G11C16/3431 , G11C29/00 , G11C29/50004 , G11C29/50008 , G11C2029/0411 , G11C2029/5002
摘要： A storage module may include a NAND-type flash memory array and one or more controllers configured to increase gate bias voltage levels applied to gates in the memory array to overcome possible gate shorts and recover data identified as being uncorrectable. The increased gate bias voltages may be applied to gates of a single type of transistor or to different types of transistors in the memory array, including drain select transistors, source select transistors, or floating gate transistors.
摘要翻译：存储模块可以包括NAND型闪存阵列和一个或多个控制器，其被配置为增加施加到存储器阵列中的栅极的栅极偏置电压电平，以克服可能的栅极短路并恢复被识别为不可校正的数据。增加的栅极偏置电压可以施加到单个晶体管的栅极或存储器阵列中的不同类型的晶体管，包括漏极选择晶体管，源极选择晶体管或浮动栅极晶体管。

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