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    • 9. 发明授权
    • Partial wafer bonding and dicing
    • 部分晶片接合和切割
    • US07078320B2
    • 2006-07-18
    • US10710880
    • 2004-08-10
    • Louis C. HsuHsichang LiuJames R. Salimeno, III
    • Louis C. HsuHsichang LiuJames R. Salimeno, III
    • H01L21/326H01L21/46
    • H01L21/2007H01L21/78Y10S438/977
    • Disclosed is a method of manufacturing integrated circuit chips that partially joins an integrated circuit wafer to a supporting wafer at a limited number of joining points. Once joined, the integrated circuit wafer is chemically-mechanically polished to reduce the thickness of the integrated circuit wafer. Then, after reducing the thickness of the integrated circuit wafer, the invention performs conventional processing on the integrated circuit wafer to form devices and wiring in the integrated circuit wafer. Next, the invention cuts through the integrated circuit wafer and the supporting wafer to form chip sections. During this cutting process, the integrated circuit wafer separates from the supporting wafer in chip sections where the integrated circuit wafer is not joined to the supporting wafer by the joining points. Chip sections where the integrated circuit wafer remains joined to the supporting wafer are thicker than the chips sections where the integrated circuit wafer separates from the supporting wafer.
    • 公开了一种制造在有限数量的接合点部分地将集成电路晶片连接到支撑晶片的集成电路芯片的方法。 一旦接合,集成电路晶片被化学机械抛光以减小集成电路晶片的厚度。 然后,在减小集成电路晶片的厚度之后,本发明对集成电路晶片进行常规处理,以在集成电路晶片中形成器件和布线。 接下来,本发明切割集成电路晶片和支撑晶片以形成芯片部分。 在该切割过程中,集成电路晶片与集成电路晶片通过接合点未接合到支撑晶片的芯片部分中的支撑晶片分离。 集成电路晶片保持接合到支撑晶片的芯片部分比集成电路晶片与支撑晶片分离的芯片部分更厚。