专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6122203A Method, architecture and circuit for writing to and reading from a memory during a single cycle 失效
标题翻译：在单个周期内写入和读取存储器的方法，架构和电路
公开(公告)号：US6122203A
公开(公告)日：2000-09-19
申请号：US107000
申请日：1998-06-29
申请人： Jeffery Scott Hunt , Sudhaker Reddy Anumula , Ajay Srikrishna , Jeffrey W. Waldrip , Satish C. Saripella
发明人： Jeffery Scott Hunt , Sudhaker Reddy Anumula , Ajay Srikrishna , Jeffrey W. Waldrip , Satish C. Saripella
IPC分类号： G11C7/22 , G11C7/00
CPC分类号： G11C7/22
摘要： A circuit and method comprising a memory, a first latch, a second latch and a control circuit. The memory may be configured to write information in response to (i) an input data signal and (ii) an address signal. The first latch may be configured to hold the address in response to a control signal. The second latch may be configured to hold the data input signal in response to the control signal. The control circuit may be configured to present the control signal in response to (i) an enable signal and (ii) a detect signal.
摘要翻译：一种包括存储器，第一锁存器，第二锁存器和控制电路的电路和方法。存储器可以被配置为响应于（i）输入数据信号和（ii）地址信号来写入信息。第一锁存器可以被配置为响应于控制信号保持地址。第二锁存器可以被配置为响应于控制信号保持数据输入信号。控制电路可以被配置为响应于（i）使能信号和（ii）检测信号来呈现控制信号。

2. 发明授权

US5986970A Method, architecture and circuit for writing to a memory 失效
标题翻译：用于写入内存的方法，架构和电路
公开(公告)号：US5986970A
公开(公告)日：1999-11-16
申请号：US106806
申请日：1998-06-29
申请人： Jeffery Scott Hunt , Sudhaker Reddy Anumula , Ajay Srikrishna , Jeffrey W. Waldrip , Satish C. Saripella
发明人： Jeffery Scott Hunt , Sudhaker Reddy Anumula , Ajay Srikrishna , Jeffrey W. Waldrip , Satish C. Saripella
IPC分类号： G11C7/10 , G11C7/22 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1039
摘要： A circuit and method comprising a memory, a first latch, a second latch and a control circuit. The memory may be configured to write information in response to (i) an input data signal and (ii) an address signal. The first latch may be configured to hold the address in response to a control signal. The second latch may be configured to hold the data input signal in response to the control signal. The control circuit may be configured to present the control signal in response to (i) a detect signal and (ii) a transition of the address signal.
摘要翻译：一种包括存储器，第一锁存器，第二锁存器和控制电路的电路和方法。存储器可以被配置为响应于（i）输入数据信号和（ii）地址信号来写入信息。第一锁存器可以被配置为响应于控制信号保持地址。第二锁存器可以被配置为响应于控制信号保持数据输入信号。控制电路可以被配置为响应于（i）检测信号和（ii）地址信号的转换来呈现控制信号。

3. 发明授权

US5978280A Method, architecture and circuit for reducing and/or eliminating small signal voltage swing sensitivity 有权
标题翻译：降低和/或消除小信号电压摆幅灵敏度的方法，架构和电路
公开(公告)号：US5978280A
公开(公告)日：1999-11-02
申请号：US132100
申请日：1998-08-10
申请人： Satish C. Saripella , Jeffery Scott Hunt , Sudhaker Reddy Anumula , Ajay Srikrishna
发明人： Satish C. Saripella , Jeffery Scott Hunt , Sudhaker Reddy Anumula , Ajay Srikrishna
IPC分类号： G11C7/06 , G11C13/00
CPC分类号： G11C7/06
摘要： A circuit comprising a sense amplifier, an evaluation circuit, a control circuit and a register circuit. The sense amplifier circuit may be configured to present a first output and a second output in response to (i) an input signal and (ii) an enable signal. The evaluation circuit may be configured to present an evaluation signal in response to the first and second outputs. The control circuit may be configured to present (i) a first clock signal, a second clock signal and an enable signal in response to (i) the evaluation signal and (ii) a wordline signal. The register circuit may be configured to hold either the first or second output in response to the first and second clock signals. The register circuit may be implemented as a master-slave register that may respond to the first and second clock signals.
摘要翻译：一种包括读出放大器，评估电路，控制电路和寄存器电路的电路。读出放大器电路可以被配置为响应于（i）输入信号和（ii）使能信号而呈现第一输出和第二输出。评估电路可以被配置为响应于第一和第二输出呈现评估信号。响应于（i）评估信号和（ii）字线信号，控制电路可以被配置为呈现（i）第一时钟信号，第二时钟信号和使能信号。寄存器电路可以被配置为响应于第一和第二时钟信号保持第一或第二输出。寄存器电路可以被实现为可响应于第一和第二时钟信号的主从寄存器。

4. 发明授权

US6016277A Reference voltage generator for reading a ROM cell in an integrated RAM/ROM memory device 失效
标题翻译：用于读取集成RAM / ROM存储器件中的ROM单元的参考电压发生器
公开(公告)号：US6016277A
公开(公告)日：2000-01-18
申请号：US884581
申请日：1997-06-27
申请人： George M. Ansel , Jeffery S. Hunt , Satish Saripella , Sudhaker Reddy Anumula , Ajay Srikrishna
发明人： George M. Ansel , Jeffery S. Hunt , Satish Saripella , Sudhaker Reddy Anumula , Ajay Srikrishna
IPC分类号： G11C11/00 , G11C7/06
CPC分类号： G11C11/005
摘要： A reference voltage generator may include an input for receiving a first voltage for input to a sense amp. The reference voltage generator may also include an output for outputting a second voltage for input to the sense amp. The second voltage is influenced by the first voltage. Alternatively, a reference voltage generator may include a first input for receiving a first voltage on a first bitline. The reference voltage generator may also include a first output for outputting a second voltage on a second bitline. The second voltage is influenced by the first voltage. Alternatively, a reference voltage generator may include a first input for receiving a first voltage on a first transmission busline. The voltage generator may also include a first output for outputting a second voltage on a second transmission busline. The second voltage is influenced by the first voltage.
摘要翻译：参考电压发生器可以包括用于接收用于输入到感测放大器的第一电压的输入端。参考电压发生器还可以包括用于输出用于输入到感测放大器的第二电压的输出。第二电压受第一电压的影响。或者，参考电压发生器可以包括用于在第一位线上接收第一电压的第一输入。参考电压发生器还可以包括用于在第二位线上输出第二电压的第一输出。第二电压受第一电压的影响。或者，参考电压发生器可以包括用于在第一传输总线上接收第一电压的第一输入。电压发生器还可以包括用于在第二传输总线上输出第二电压的第一输出。第二电压受第一电压的影响。

5. 发明授权

US5880999A Read only/random access memory architecture and methods for operating same 失效
标题翻译：只读/随机访问存储器架构和操作方法
公开(公告)号：US5880999A
公开(公告)日：1999-03-09
申请号：US884561
申请日：1997-06-27
申请人： George M. Ansel , Jeffery S. Hunt , Satish Saripella , Sudhaker Reddy Anumula , Ajay Srikrishna
发明人： George M. Ansel , Jeffery S. Hunt , Satish Saripella , Sudhaker Reddy Anumula , Ajay Srikrishna
IPC分类号： G11C11/00 , G11C16/04
CPC分类号： G11C11/005
摘要： A memory device includes a random access memory (RAM) cell accessible through a RAM wordline and coupled between first and second bitlines; a read only memory (ROM) cell accessible through a ROM wordline and having an output coupled to the first bitline and an input configured to receive a first voltage signal; and a reference voltage generator having a first input coupled to the first bitline, a second input configured to receive the first voltage signal, and an output coupled to the second bitline. The memory device may further include a bitline load having an output coupled to the first bitline. A virtual ground driver configured to produce the first voltage signal may be coupled to the input of the read only memory cell. Further, column select pass gates configured to be under the control of a logic signal and having a first input coupled to the first bitline, a second input coupled to the second bitline, a first output and a second output may be provided. A sense amplifier having a first input coupled to the first output of the column select pass gates and a second input coupled to the second output of the column select pass gates may be included in the memory device. The memory device may be read by modulating a first voltage input to the sense amplifier using a second voltage input to the sense amplifier.
摘要翻译：存储器件包括通过RAM字线可访问并耦合在第一和第二位线之间的随机存取存储器（RAM）单元; 只读存储器（ROM）单元，可通过ROM字线访问并且具有耦合到第一位线的输出和被配置为接收第一电压信号的输入; 以及参考电压发生器，其具有耦合到第一位线的第一输入，被配置为接收第一电压信号的第二输入和耦合到第二位线的输出。存储器件还可以包括具有耦合到第一位线的输出的位线负载。配置为产生第一电压信号的虚拟接地驱动器可以耦合到只读存储器单元的输入。此外，列选择通道门被配置为处于逻辑信号的控制下，并且具有耦合到第一位线的第一输入，耦合到第二位线的第二输入，第一输出和第二输出。具有耦合到列选择通过门的第一输出的第一输入和耦合到列选择通道的第二输出的第二输入的读出放大器可以包括在存储器件中。可以通过使用输入到读出放大器的第二电压调制对读出放大器的第一电压输入来读取存储器件。

6. 发明授权

US07461200B1 Method and apparatus for overlaying flat and tree based data sets onto content addressable memory (CAM) device 有权
标题翻译：将平面和基于树的数据集覆盖到内容寻址存储器（CAM）装置上的方法和装置
公开(公告)号：US07461200B1
公开(公告)日：2008-12-02
申请号：US10950323
申请日：2004-09-23
申请人： Mark Birman , Ajay Srikrishna , Srinivasan Venkatachary
发明人： Mark Birman , Ajay Srikrishna , Srinivasan Venkatachary
IPC分类号： G06F12/00
CPC分类号： G11C15/00 , Y10S707/99936
摘要： A content addressable memory device (100) and method can have CAM blocks (102-0 to 102-29) organized in block sections (104-0 to 104-6). In an overlay mode of operation, an overlay engine (106) can access an algorithmic search (SPEAR) CAM (102-28 and 102-29) to generate overlay data set search keys (keyFIB and ). Multiple data sets (e.g., FIB0, FIB1, ACL0) can be accommodated on the same CAM device by search key multiplexers (108-0 to 108-6) that selectively apply any of a number of data set search keys (keyACL , keyFIB and keyFIB ).
摘要翻译：内容可寻址存储器件（100）和方法可以具有以块部分（104-0至104-6）组织的CAM块（102-0至102-29）。在覆盖操作模式中，覆盖引擎（106）可以访问算法搜索（SPEAR）CAM（102-28和102-29）以生成覆盖数据集搜索关键字（keyFIB <0>和<1>）。多个数据集（例如，FIB0，FIB1，ACL0）可以通过搜索关键多路复用器（108-0至108-6）容纳在相同的CAM设备上，该多路复用器选择性地应用多个数据集搜索键（keyACL < ，keyFIB <0>和keyFIB <1>）。

7. 发明授权

US07836246B2 Method and apparatus for overlaying flat and/or tree based data sets onto content addressable memory (CAM) device 失效
标题翻译：用于将平面和/或基于树的数据集覆盖到内容可寻址存储器（CAM）设备上的方法和装置
公开(公告)号：US07836246B2
公开(公告)日：2010-11-16
申请号：US12214952
申请日：2008-06-23
申请人： Mark Birman , Ajay Srikrishna , Srinivasan Venkatachary
发明人： Mark Birman , Ajay Srikrishna , Srinivasan Venkatachary
IPC分类号： G06F13/00
CPC分类号： G11C15/00 , Y10S707/99936
摘要： A content addressable memory device (100) and method can have CAM blocks (102-0 to 102-29) organized in block sections (104-0 to 104-6). In an overlay mode of operation, an overlay engine (106) can access an algorithmic search (SPEAR) CAM (102-28 and 102-29) to generate overlay data set search keys (keyFIB and ). Multiple data sets (e.g., FIB0, FIB1, ACL0) can be accommodated on the same CAM device by search key multiplexers (108-0 to 108-6) that selectively apply any of a number of data set search keys (keyACL , keyFIB and keyFIB ).
摘要翻译：内容可寻址存储器件（100）和方法可以具有以块部分（104-0至104-6）组织的CAM块（102-0至102-29）。在覆盖操作模式中，覆盖引擎（106）可以访问算法搜索（SPEAR）CAM（102-28和102-29）以生成覆盖数据集搜索关键字（keyFIB <0>和<1>）。多个数据集（例如，FIB0，FIB1，ACL0）可以通过搜索关键多路复用器（108-0至108-6）容纳在相同的CAM设备上，该多路复用器选择性地应用多个数据集搜索键（keyACL < ，keyFIB <0>和keyFIB <1>）。

8. 发明授权

US07451267B1 Method and apparatus for learn and related operations in network search engine 有权
标题翻译：网络搜索引擎中学习和相关操作的方法和装置
公开(公告)号：US07451267B1
公开(公告)日：2008-11-11
申请号：US10948050
申请日：2004-09-22
申请人： Srinivasan Venkatachary , Ajay Srikrishna , Jagadeesan Rajamanickam
发明人： Srinivasan Venkatachary , Ajay Srikrishna , Jagadeesan Rajamanickam
IPC分类号： G06F12/00
CPC分类号： G11C15/00
摘要： A search engine method and apparatus can store and update status information for each entry of a content addressable memory (CAM) array, for a learn operation, or the like. A search engine can include a status memory block external to and independent of the CAM array. A status memory block (800) can include a number of memory sections (806-0 to 806-2) that each includes a number of bit locations for storing a free/not-free status of CAM entries in a hierarchical fashion. Corresponding control sections (808-0 to 808-2) can include priority encoders (812-0 to 812-2) that determine a first free element in a memory section for a next hierarchical level, as well as status aggregation logic (814-0 to 814-2) that can generate an aggregated status that is propagated to a previous hierarchical level.
摘要翻译：搜索引擎方法和装置可以存储和更新用于学习操作等的内容可寻址存储器（CAM）阵列的每个条目的状态信息。搜索引擎可以包括外部并独立于CAM阵列的状态存储器块。状态存储器块（800）可以包括多个存储器部分（806-0至806-2），每个存储器部分包括用于以分级方式存储CAM条目的空闲/不自由状态的多个位位置。相应的控制部分（808-0至808-2）可以包括确定用于下一层级的存储器部分中的第一空闲元素的优先编码器（812-0至812-2）以及状态聚合逻辑（814- 0到814-2），其可以生成被传播到先前分层级的聚合状态。

9. 发明申请

US20080263270A1 Method and apparatus for overlaying flat and/or tree based data sets onto content addressable memory (CAM) device 失效
标题翻译：用于将平面和/或基于树的数据集覆盖到内容可寻址存储器（CAM）设备上的方法和装置
公开(公告)号：US20080263270A1
公开(公告)日：2008-10-23
申请号：US12214952
申请日：2008-06-23
申请人： Mark Birman , Ajay Srikrishna , Srinivasan Venkatachary
发明人： Mark Birman , Ajay Srikrishna , Srinivasan Venkatachary
IPC分类号： G06F12/00
CPC分类号： G11C15/00 , Y10S707/99936
摘要： A content addressable memory device (100) and method can have CAM blocks (102-0 to 102-29) organized in block sections (104-0 to 104-6). In an overlay mode of operation, an overlay engine (106) can access an algorithmic search (SPEAR) CAM (102-28 and 102-29) to generate overlay data set search keys (keyFIB and ). Multiple data sets (e.g., FIB0, FIB1, ACL0) can be accommodated on the same CAM device by search key multiplexers (108-0 to 108-6) that selectively apply any of a number of data set search keys (keyACL , keyFIB and keyFIB ).
摘要翻译：内容可寻址存储器件（100）和方法可以具有以块部分（104-0至104-6）组织的CAM块（102-0至102-29）。在覆盖操作模式中，覆盖引擎（106）可以访问算法搜索（SPEAR）CAM（102-28和102-29）以产生覆盖数据集搜索关键字（keyFIB <0>和<1>）。多个数据集（例如，FIB 0，FIB 1，ACL 0）可以通过搜索关键多路复用器（108-0至108-6）容纳在相同的CAM设备上，该多路复用器选择性地应用多个数据集搜索键（keyACL <0>，keyFIB <0>和keyFIB <1>）。

10. 发明授权

US06958925B1 Staggered compare architecture for content addressable memory (CAM) device 失效
标题翻译：内容可寻址内存（CAM）设备的交错比较架构
公开(公告)号：US06958925B1
公开(公告)日：2005-10-25
申请号：US10746899
申请日：2003-12-24
申请人： Hari Om , Ajay Srikrishna , Nabil N. Masri
发明人： Hari Om , Ajay Srikrishna , Nabil N. Masri
IPC分类号： G11C15/00 , G11C15/04
CPC分类号： G11C15/00
摘要： A content addressable memory (CAM) device (300) can receive a compare data value having a native word size. The compare data value can be split into smaller portions, with one portion can be applied to a first CAM block (302-0) and another being applied to a second CAM block (302-1) on a subsequent clock (CAMCLK) cycle. Activation of circuit elements in the second CAM block (302-1) can be conditioned on first match results (CMATCHA0 to CMATCHAn) generated by first CAM block (302-0).
摘要翻译：内容可寻址存储器（CAM）设备（300）可以接收具有本机字大小的比较数据值。比较数据值可以被分割成更小的部分，其中一个部分可以应用于第一CAM块（302-0），而另一个部分可以应用到后续时钟（CAMCLK）周期上的第二CAM块（302-1）。第二CAM块（302-1）中的电路元件的激活可以由第一CAM块（302-1）产生的第一匹配结果（CMATCHA 到CMATCHA 0）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式