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1. 发明授权

US5339417A Computer system with two levels of guests 失效
标题翻译：计算机系统与两级客人
公开(公告)号：US5339417A
公开(公告)日：1994-08-16
申请号：US77819
申请日：1993-06-16
申请人： Jefferson J. Connell , Vernon R. Johnson , Peter H. Lipman , Robert M. Maier
发明人： Jefferson J. Connell , Vernon R. Johnson , Peter H. Lipman , Robert M. Maier
IPC分类号： G06F9/455 , G06F9/06
CPC分类号： G06F9/45558 , G06F2009/45566
摘要： A computer system having a chief system control program running in a real machine as a host where the host controls standard system control programs (SCP's) and controls virtual machines (Domains) called guests. Guests operate with interpretive execution as second-level guests. Control is transferred from a second-level guest to the guest SCP or to the chief SCP with only one control interception. Control is transferred directly between the second-level guest and the Chief SCP bypassing the first-level guest.
摘要翻译：一种计算机系统，其主系统控制程序在主机中作为主机运行，主机控制标准系统控制程序（SCP）并控制称为客户机的虚拟机（域）。客人作为二级客人进行解释性执行。控制从二级客人转移到客人SCP或主控SCP，只有一个控制拦截。控制权直接在二级客人和首席执行官之间直接转移，绕过一级客人。

2. 发明授权

US5459872A Software control of hardware interruptions 失效
标题翻译：软件控制硬件中断
公开(公告)号：US5459872A
公开(公告)日：1995-10-17
申请号：US152906
申请日：1993-11-15
申请人： Jefferson J. Connell , Vernon R. Johnson , Peter H. Lipman , Robert M. Maier
发明人： Jefferson J. Connell , Vernon R. Johnson , Peter H. Lipman , Robert M. Maier
IPC分类号： G06F13/24 , G06F9/46
CPC分类号： G06F13/24
摘要： In a computer system including an interrupt processor for interrupting a program being processed by the computer system, a sub-system for processing interrupt requests to the interrupt processor. The sub-system comprises hardware circuit for generating hardware interrupt requests and control circuit for implementing control software where the control software causing software interrupt requests to be generated by said control circuit. An interrupt register stores and identifies both the hardware and software interrupt requests. A selection circuit selects and sends one of said stored interrupt request stored in the interrupt register to the interrupt processor for processing. The control circuit, under control of the control software, generates an end software interrupt requests for removing software interrupt request stored in the interrupt register such that software interrupt in the computer system can be generated and terminated under the control of the control software.
摘要翻译：在包括用于中断由计算机系统处理的程序的中断处理器的计算机系统中，用于处理对中断处理器的中断请求的子系统。该子系统包括用于产生硬件中断请求的硬件电路和用于实现控制软件的控制电路，其中由所述控制电路产生软件中断请求的控制软件。中断寄存器存储并识别硬件和软件中断请求。选择电路将存储在中断寄存器中的所述存储的中断请求之一选择并发送到中断处理器进行处理。控制电路在控制软件的控制下，产生一个终止软件中断请求，用于去除存储在中断寄存器中的软件中断请求，使得计算机系统中的软件中断可以在控制软件的控制下生成和终止。

3. 发明授权

US07370243B1 Precise error handling in a fine grain multithreaded multicore processor 有权
标题翻译：精细多线程多核处理器中的精确错误处理
公开(公告)号：US07370243B1
公开(公告)日：2008-05-06
申请号：US10881111
申请日：2004-06-30
申请人： Gregory F. Grohoski , Ricky C. Hetherington , Paul J. Jordan , Robert M. Maier
发明人： Gregory F. Grohoski , Ricky C. Hetherington , Paul J. Jordan , Robert M. Maier
IPC分类号： G06F11/00
CPC分类号： G06F11/0772 , G06F9/3851 , G06F9/3865 , G06F9/3891 , G06F11/0721 , G06F11/0724 , G06F11/0781
摘要： A method and mechanism for error recovery in a processor. A multithreaded processor is configured to utilize software for hardware detected machine errors. Rather than correcting and clearing the detected errors, hardware is configured to report the errors precisely. Both program-related exceptions and hardware errors are detected and, without being corrected by the hardware, flow down the pipeline to a trap unit where they are prioritized and handled via software. The processor assigns each instruction a thread ID and error information as it follows the pipeline. The trap unit records the error by using the thread ID of the instruction and the pipelined error information in order to determine which ESR receives the information and what to store in the ESR. A trap handling routine is then initiated to facilitate error recovery.
摘要翻译：一种处理器中错误恢复的方法和机制。多线程处理器配置为利用软件检测到机器错误。硬件不是纠正和清除检测到的错误，而是配置为精确地报告错误。检测到与程序相关的异常和硬件错误，并且在不被硬件校正的情况下，将流水线下流到陷阱单元，并通过软件进行优先处理。处理器为每个指令分配线程ID和错误信息，因为它遵循流水线。陷阱单元通过使用指令的线程ID和流水线错误信息记录错误，以确定哪个ESR接收信息以及在ESR中存储的内容。然后启动陷阱处理例程以促进错误恢复。

4. 发明授权

US4888689A Apparatus and method for improving cache access throughput in pipelined processors 失效
标题翻译：用于提高流水线处理器中缓存访问吞吐量的装置和方法
公开(公告)号：US4888689A
公开(公告)日：1989-12-19
申请号：US920805
申请日：1986-10-17
申请人： Michael D. Taylor , Robert M. Maier , Michael J. Begley , Allan J. Zmyslowski , Jeffrey A. Thomas , Joseph A. Petolino
发明人： Michael D. Taylor , Robert M. Maier , Michael J. Begley , Allan J. Zmyslowski , Jeffrey A. Thomas , Joseph A. Petolino
IPC分类号： G06F9/38
CPC分类号： G06F9/383
摘要： An apparatus and method for use in improving cache storage unit utilization during an interlock of an instruction pipeline generates a control signal during one cycle of the interlock if the interlocked instruction may require storage unit management work. In response to the control signal, selector control logic in the storage unit generates a priority signal indicating the interlocked instruction for selection by the storage unit for processing. In response to the control signal and the priority signal, the cache management logic is used during the interlock on the interlocked instruction to prepare for supplying needed data when the interlock is released.
摘要翻译：如果联锁指令可能需要存储单元管理工作，则用于在指令流水线的互锁期间用于提高高速缓存存储单元利用率的装置和方法在互锁的一个周期期间生成控制信号。响应于控制信号，存储单元中的选择器控制逻辑产生指示由存储单元进行选择的互锁指令的优先信号进行处理。响应于控制信号和优先级信号，在互锁指令的互锁期间使用高速缓存管理逻辑来准备在互锁被释放时提供所需数据。

5. 发明授权

US5210832A Multiple domain emulation system with separate domain facilities which tests for emulated instruction exceptions before completion of operand fetch cycle 失效
标题翻译：多域仿真系统具有单独的域设备，可在完成操作数提取周期之前对仿真指令异常进行测试
公开(公告)号：US5210832A
公开(公告)日：1993-05-11
申请号：US725905
申请日：1991-07-03
申请人： Robert M. Maier , John C. Andoh , Arno S. Krakauer , Richard J. Tobias , Allan J. Zmyslowski
发明人： Robert M. Maier , John C. Andoh , Arno S. Krakauer , Richard J. Tobias , Allan J. Zmyslowski
IPC分类号： G06F9/318
CPC分类号： G06F9/3017
摘要： In a data processing apparatus, having a user domain with domain storage space and an emulation domain with emulation storage space, emulates an instruction in the user domain by calling a program of instructions in the emulation domain. An instruction register connected to receive the sequence of instructions is partitioned into a plurality of fields. At least one field of the instruction register identifies a location for address information for an operand used in execution of the instruction. The instruction is decoded to generate a control code. The control code includes a branch signal to call the emulation program and a domain access control signal to indicate whether the emulation program requires access to the user domain storage base for execution. During execution of the emulation routine, domain access is implied by the location identified for the address information--a set of locations having been preselected as address registers for implied domain addressing.
摘要翻译：在具有域存储空间的用户域和具有仿真存储空间的仿真域的数据处理装置中，通过调用仿真域中的指令程序来模拟用户域中的指令。连接以接收指令序列的指令寄存器被划分为多个字段。指令寄存器的至少一个字段标识用于执行指令的操作数的地址信息的位置。该指令被解码以产生控制码。控制代码包括调用仿真程序的分支信号和域访问控制信号，以指示仿真程序是否需要访问用户域存储库以供执行。在仿真程序的执行期间，由地址信息标识的位置暗示了域访问 - 一组已被预选为隐含域寻址的地址寄存器的位置。

6. 发明授权

US4785392A Addressing multiple storage spaces 失效
标题翻译：寻址多个存储空间
公开(公告)号：US4785392A
公开(公告)日：1988-11-15
申请号：US918491
申请日：1986-10-14
申请人： Robert M. Maier , John C. Andoh , Arno S. Krakauer , Richard J. Tobias , Allan J. Zmyslowski
发明人： Robert M. Maier , John C. Andoh , Arno S. Krakauer , Richard J. Tobias , Allan J. Zmyslowski
IPC分类号： G06F9/455 , G06F9/46 , G06F12/00
CPC分类号： G06F9/45558 , G06F2009/45579
摘要： In a data processing apparatus, having a user domain with domain storage space and an emulation domain with emulation storage space, emulates an instruction in the user domain by calling a program of instructions in the emulation domain. An instruction register connected to receive the sequence of instructions is partitioned into a plurality of fields. At least one field of the instruction register identifies a location for address information for an operand used in execution of the instruction. The instruction is decoded to generate a control code. The control code includes a branch signal to call the emulation program and a domain access control signal to indicate whether the emulation program requires access to the user domain storage base for execution. During execution of the emulation routine, domain access is implied by the location identified for the address information--a set of locations having been preselected as address registers for implied domain addressing.
摘要翻译：在具有域存储空间的用户域和具有仿真存储空间的仿真域的数据处理装置中，通过调用仿真域中的指令程序来模拟用户域中的指令。连接以接收指令序列的指令寄存器被划分为多个字段。指令寄存器的至少一个字段标识用于执行指令的操作数的地址信息的位置。该指令被解码以产生控制码。控制代码包括调用仿真程序的分支信号和域访问控制信号，以指示仿真程序是否需要访问用户域存储库以供执行。在仿真程序的执行期间，由地址信息标识的位置暗示了域访问 - 一组已被预选为隐含域寻址的地址寄存器的位置。

7. 发明授权

US4855947A Microprogrammable pipeline interlocks based on the validity of pipeline states 失效
标题翻译：基于管道状态有效性的微程序管道互锁
公开(公告)号：US4855947A
公开(公告)日：1989-08-08
申请号：US54947
申请日：1987-05-27
申请人： Allan J. Zmyslowski , Robert M. Maier
发明人： Allan J. Zmyslowski , Robert M. Maier
IPC分类号： G06F9/28 , G06F9/38
CPC分类号： G06F9/3873 , G06F9/28 , G06F9/3867
摘要： An interlock of an instruction processing pipeline in a data processing system responsive to the validity of the pipeline stages within the instruction unit pipeline under microprogram control, is provided. Thus, a microprogram can provide for the release of a particular pipeline stage based on a selected characteristic of the valid signals generated by other stages of the pipeline. An interlock control signal is generated by a decode of a field in a microinstruction stored in a control store RAM or through hardwired decoding.
摘要翻译：提供了在微程序控制下响应于指令单元管线内的流水线级的有效性的数据处理系统中的指令处理流水线的互锁。因此，微程序可以基于由管道的其它级产生的有效信号的选定特性来提供特定流水线级的释放。通过存储在控制存储器RAM中的微指令中的字段的解码或通过硬连线解码来生成互锁控制信号。

8. 发明授权

US4812989A Method for executing machine language instructions 失效
标题翻译：执行机器语言指令的方法
公开(公告)号：US4812989A
公开(公告)日：1989-03-14
申请号：US919208
申请日：1986-10-15
申请人： Robert M. Maier , Allan J. Zmyslowski , Carolee N. Schober
发明人： Robert M. Maier , Allan J. Zmyslowski , Carolee N. Schober
IPC分类号： G06F9/26 , G06F7/00 , G06F9/28
CPC分类号： G06F9/261
摘要： The present invention provides for use in a data processor a method for mapping a respective machine language instruction stored by cache storage unit to a respective microprogrammed algorithm stored in control storage unit means, wherein the respective machine language instruction includes an opcode field with a prescribed value and at least one nonopcode field with one of a plurality of values, the method, comprising the steps of in the course of one data processor clock cycle, providing the respective machine language instruction to a decoder for converting the prescribed opcode field and the at least one nonopcode field of the respective machine language instruction into a respective combination of decoded signals which corresponds to the prescribed opcode field value and that at least one nonopcode field value of the respective machine language instruction; and providing the respective combination of decoded signals to combinational logic for converting the respective combination of decode signals into a respective address signal which points to a microprogrammed algorithm stored by the control storage unit means.
摘要翻译：本发明提供在数据处理器中使用的方法，用于将由高速缓存存储单元存储的相应的机器语言指令映射到存储在控制存储单元装置中的相应的微程序化算法，其中相应的机器语言指令包括具有规定值的操作码字段以及至少一个具有多个值中的一个值的非代码字段，所述方法包括以下步骤：在一个数据处理器时钟周期的过程中，将相应的机器语言指令提供给解码器，用于将规定的操作码字段和至少将相应的机器语言指令的一个非代码字段转换成对应于规定的操作码字段值的解码信号和相应的机器语言指令的至少一个非代码字段值的相应组合; 以及将解码信号的相应组合提供给组合逻辑，用于将解码信号的相应组合转换成指向由控制存储单元装置存储的微程序化算法的相应地址信号。

9. 发明授权

US4661953A Error tracking apparatus in a data processing system 失效
标题翻译：数据处理系统中的误差跟踪装置
公开(公告)号：US4661953A
公开(公告)日：1987-04-28
申请号：US907131
申请日：1986-09-12
申请人： Venkatramiah Venkatesh , Robert M. Maier
发明人： Venkatramiah Venkatesh , Robert M. Maier
IPC分类号： G06F11/07 , G06F11/00
CPC分类号： G06F11/0772
摘要： Disclosed is an error-tracking unit within a data processing system. Each data location to be checked for error and to be located in the case of an error is provided with error detection circuitry. Each data location is additionally provided with an error history register for storing an error signal. When the error-detecting circuit detects an error, the error history register is enabled to store the error signal. Whenever an error is detected, the error history registers are inhibited from further change so that errors are not propagated. The error detection also causes a machine check signal which, in general, prevents the data processing system from normal processing.
摘要翻译：公开了数据处理系统内的错误跟踪单元。错误检测电路提供要检查错误的每个数据位置和位于错误情况下的位置。每个数据位置还附有一个用于存储错误信号的错误历史寄存器。当错误检测电路检测到错误时，错误历史寄存器被使能以存储错误信号。无论何时检测到错误，将禁止错误历史寄存器进一步更改，从而不会传播错误。错误检测还导致机器检查信号，其通常防止数据处理系统正常处理。

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