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1. 发明授权

US07833908B2 Slurry composition for chemical-mechanical polishing capable of compensating nanotopography effect and method for planarizing surface of semiconductor device using the same 有权
标题翻译：用于补偿纳米形貌效果的化学机械抛光的浆料组合物及使用其的半导体器件的平坦化表面的方法
公开(公告)号：US07833908B2
公开(公告)日：2010-11-16
申请号：US10556377
申请日：2004-05-11
申请人： Jea Gun Park , Takeo Katoh , Won Mo Lee , Hyun Goo Kang , Sung Jun Kim , Un Gyu Paik
发明人： Jea Gun Park , Takeo Katoh , Won Mo Lee , Hyun Goo Kang , Sung Jun Kim , Un Gyu Paik
IPC分类号： H01L21/302
CPC分类号： C09G1/02 , H01L21/31053
摘要： A slurry composition for chemical-mechanical polishing capable of compensating nanotopography effect present on the surface of a wafer, and a method for planarizing the surface of a semiconductor device that utilizes the same are disclosed. The slurry composition of the present invention is aimed at compensating the nanotopography effect during chemical mechanical polishing process of the oxide layer formed on the surface of the wafer, and contains abrasive particles and an additive, wherein the size of the abrasive particles and the concentration of the additive are controlled within predetermined ranges in order to control the deviation of thickness (OTD) of the oxide layer below a certain level after the chemical mechanical polishing process.
摘要翻译：公开了一种能够补偿晶片表面上存在的纳米形貌效应的用于化学机械抛光的浆料组合物，以及用于平面化利用其的半导体器件的表面的方法。本发明的浆料组合物旨在补偿在晶片表面形成的氧化物层的化学机械抛光过程中的纳米形貌作用，并且包含磨料颗粒和添加剂，其中磨料颗粒的尺寸和浓度将添加剂控制在预定范围内，以便在化学机械抛光处理之后控制氧化物层的厚度（OTD）低于一定水平的偏差。

2. 发明授权

US07344973B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07344973B2
公开(公告)日：2008-03-18
申请号：US11265683
申请日：2005-11-02
申请人： Kyung Ho Hwang , Won Mo Lee
发明人： Kyung Ho Hwang , Won Mo Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76877 , H01L21/7684 , H01L21/76895 , H01L21/823475
摘要： Provided are a semiconductor device, adapted to be capable of fabricating the device having improved resistance characteristic by decreasing dishing of solid phase epitaxy (SPE) silicon during planarization in a landing plug forming process via use of SPE silicon, and a method of manufacturing the same.The method of manufacturing a semiconductor device in accordance with the present invention comprises, forming a plurality of gates on a semiconductor substrate; forming an interlayer dielectric film thereon, such that the gates are embedded; selectively etching the interlayer dielectric film to open a landing plug-forming region; depositing SPE silicon, such that the opened landing plug-forming region in the interlayer dielectric film is embedded; implanting boron ions into the SPE silicon; and annealing the resulting boron ion-implanted structure.
摘要翻译：提供一种半导体器件，其适于能够通过使用SPE硅在着陆塞形成过程中的平坦化期间减少固相外延（SPE）硅的凹陷来制造具有改进的电阻特性的器件及其制造方法。根据本发明的制造半导体器件的方法包括：在半导体衬底上形成多个栅极; 在其上形成层间电介质膜，使得栅极被嵌入; 选择性地蚀刻层间电介质膜以打开着陆堵塞形成区域; 沉积SPE硅，使得层间绝缘膜中的开放的着色塞形成区被嵌入; 将硼离子注入SPE硅中; 并对所得的硼离子注入结构进行退火。

3. 发明授权

US07265054B2 Chemical mechanical polishing method for manufacturing semiconductor device 失效
标题翻译：化学机械抛光方法制造半导体器件
公开(公告)号：US07265054B2
公开(公告)日：2007-09-04
申请号：US11268961
申请日：2005-11-08
申请人： Yong Soo Choi , Won Mo Lee
发明人： Yong Soo Choi , Won Mo Lee
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/3212
摘要： Disclosed herein is a chemical mechanical polishing (CMP) method for manufacturing a semiconductor device, comprising performing partial ion implantation of dopants at different concentrations into a plurality of at least two divided regions of a wafer having a planarization-target film, and subjecting the partially ion implanted-wafer to a chemical mechanical polishing process. In accordance with the present invention, non-uniformity of the removal rate in a chemical mechanical polishing process is countervailed by dopants which are implanted at different concentrations via partial ion implantation, and thereby it is possible to polish the target film at a uniform removal rate.
摘要翻译：本文公开了一种用于制造半导体器件的化学机械抛光（CMP）方法，包括：将具有不同浓度的掺杂剂的部分离子注入到具有平坦化靶膜的晶片的多个至少两个分割区域中，离子注入晶片进行化学机械抛光工艺。根据本发明，化学机械抛光工艺中的去除速率的不均匀性被通过部分离子注入以不同浓度注入的掺杂剂抵消，从而可以以均匀的去除速率对目标膜进行抛光。

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