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1. 发明申请

US20090224254A1 THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20090224254A1
公开(公告)日：2009-09-10
申请号：US12417280
申请日：2009-04-02
申请人： Je-Hun LEE , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
发明人： Je-Hun LEE , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
IPC分类号： H01L27/06 , H01L33/00 , H01L29/786
CPC分类号： G02F1/13439 , G02F1/13458 , H01L27/12 , H01L27/124 , H01L29/458 , H01L29/4908
摘要： A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn in which the rmetal component is reduced in the IZO, ITO, or a-ITO is not produced on the surfaces of the common electrode.
摘要翻译：提供了薄膜晶体管阵列面板，其包括基板，形成在基板上的多个栅极线，在基板上具有透明导电层的多个公共电极，覆盖栅极线和公共电极的栅极绝缘层形成在所述栅极绝缘层上的多个半导体层，形成在所述半导体层和所述栅极绝缘层上的多个源极电极的多条数据线，形成在所述半导体层上的多个漏电极和所述栅极绝缘体并且与公共电极重叠并连接到漏电极的多个像素电极。由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生在IZO，ITO或ITO中还原金属成分的不透明金属Sn或Zn。

2. 发明申请

US20060108587A1 Thin film transistor array panel and manufacturing method thereof 失效
公开(公告)号：US20060108587A1
公开(公告)日：2006-05-25
申请号：US11260017
申请日：2005-10-26
申请人： Je-Hun Lee , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
发明人： Je-Hun Lee , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
IPC分类号： H01L29/04
CPC分类号： G02F1/13439 , G02F1/13458 , H01L27/12 , H01L27/124 , H01L29/458 , H01L29/4908
摘要： A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn in which the metal component is reduced in the IZO, ITO, or a-ITO is not produced on the surfaces of the common electrode.

3. 发明授权

US08455277B2 Thin film transistor array panel and manufacturing method thereof 失效
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US08455277B2
公开(公告)日：2013-06-04
申请号：US13523767
申请日：2012-06-14
申请人： Je-Hun Lee , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
发明人： Je-Hun Lee , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
IPC分类号： H01L21/84
CPC分类号： G02F1/13439 , G02F1/13458 , H01L27/12 , H01L27/124 , H01L29/458 , H01L29/4908
摘要： A thin film transistor array panel is provided, which includes a plurality of gate lines, a plurality of common electrodes, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer, a plurality of drain electrodes formed on the semiconductor layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn is not produced on the surfaces of the common electrode.
摘要翻译：提供薄膜晶体管阵列面板，其包括多个栅极线，多个公共电极，覆盖栅极线和公共电极的栅极绝缘层，形成在栅极绝缘层上的多个半导体层，多个包括多个源电极并形成在半导体层上的数据线，形成在半导体层上的多个漏电极以及与公共电极重叠并连接到漏电极的多个像素电极。由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生不透明金属Sn或Zn。

4. 发明授权

US08288771B2 Thin film transistor array panel and manufacturing method thereof 有权
公开(公告)号：US08288771B2
公开(公告)日：2012-10-16
申请号：US13204553
申请日：2011-08-05
申请人： Je-Hun Lee , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
发明人： Je-Hun Lee , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
IPC分类号： H01L29/786 , H01L21/336 , H01L21/84
CPC分类号： G02F1/13439 , G02F1/13458 , H01L27/12 , H01L27/124 , H01L29/458 , H01L29/4908
摘要： A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn in which the metal component is reduced in the IZO, ITO, or a-ITO is not produced on the surfaces of the common electrode.

5. 发明授权

US08207534B2 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US08207534B2
公开(公告)日：2012-06-26
申请号：US12417280
申请日：2009-04-02
申请人： Je-Hun Lee , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
发明人： Je-Hun Lee , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
IPC分类号： H01L29/786
CPC分类号： G02F1/13439 , G02F1/13458 , H01L27/12 , H01L27/124 , H01L29/458 , H01L29/4908
摘要： A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn in which the metal component is reduced in the IZO, ITO, or a-ITO is not produced on the surfaces of the common electrode.
摘要翻译：提供薄膜晶体管阵列面板，其包括基板，形成在基板上的多个栅极线，在基板上具有透明导电层的多个公共电极，覆盖栅极线和公共电极的栅极绝缘层形成在所述栅极绝缘层上的多个半导体层，形成在所述半导体层和所述栅极绝缘层上的多个源极电极的多条数据线，形成在所述半导体层上的多个漏电极和所述栅极绝缘体并且与公共电极重叠并连接到漏电极的多个像素电极。由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生在IZO，ITO或ITO中还原金属成分的不透明金属Sn或Zn。

6. 发明申请

US20110284857A1 THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20110284857A1
公开(公告)日：2011-11-24
申请号：US13204553
申请日：2011-08-05
申请人： Je-Hun LEE , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
发明人： Je-Hun LEE , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
IPC分类号： H01L27/088 , H01L21/84
CPC分类号： G02F1/13439 , G02F1/13458 , H01L27/12 , H01L27/124 , H01L29/458 , H01L29/4908
摘要： A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn in which the rmetal component is reduced in the IZO, ITO, or a-ITO is not produced on the surfaces of the common electrode.
摘要翻译：提供薄膜晶体管阵列面板，其包括基板，形成在基板上的多个栅极线，在基板上具有透明导电层的多个公共电极，覆盖栅极线和公共电极的栅极绝缘层形成在所述栅极绝缘层上的多个半导体层，形成在所述半导体层和所述栅极绝缘层上的多个源极电极的多条数据线，形成在所述半导体层上的多个漏电极和所述栅极绝缘体并且与公共电极重叠并连接到漏电极的多个像素电极。由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生在IZO，ITO或ITO中还原金属成分的不透明金属Sn或Zn。

7. 发明授权

US07527992B2 Thin film transistor array panel and manufacturing method thereof 失效
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07527992B2
公开(公告)日：2009-05-05
申请号：US11260017
申请日：2005-10-26
申请人： Je-Hun Lee , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
发明人： Je-Hun Lee , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
IPC分类号： H01L21/84
CPC分类号： G02F1/13439 , G02F1/13458 , H01L27/12 , H01L27/124 , H01L29/458 , H01L29/4908
摘要： A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn in which the metal component is reduced in the IZO, ITO, or a-ITO is not produced on the surfaces of the common electrode.
摘要翻译：提供薄膜晶体管阵列面板，其包括基板，形成在基板上的多个栅极线，在基板上具有透明导电层的多个公共电极，覆盖栅极线和公共电极的栅极绝缘层形成在所述栅极绝缘层上的多个半导体层，形成在所述半导体层和所述栅极绝缘层上的多个源极电极的多条数据线，形成在所述半导体层上的多个漏电极和所述栅极绝缘体并且与公共电极重叠并连接到漏电极的多个像素电极。由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生在IZO，ITO或ITO中还原金属成分的不透明金属Sn或Zn。

8. 发明授权

US08305326B2 Gate driving circuit having improved tolerance to gate voltage ripple and display device having the same 有权
标题翻译：栅极驱动电路具有改善的对栅极电压纹波的容限和具有其的显示器件
公开(公告)号：US08305326B2
公开(公告)日：2012-11-06
申请号：US12218814
申请日：2008-07-18
申请人： Sung-Man Kim , Hong-Woo Lee , Myung-Koo Hur , Hee-Joon Kim
发明人： Sung-Man Kim , Hong-Woo Lee , Myung-Koo Hur , Hee-Joon Kim
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G2310/0286 , G11C19/184
摘要： A gate driving circuit and a display device having the same, a pull-up unit pulls up a current gate signal by using a first clock signal during a first period of one frame. A pull-up driver coupled to the pull-up unit receives a carry signal from one of the previous stages to turn on the pull-up unit. A pull-up unit receives a gate signal from one of the next stages, discharges the current gate signal to an off voltage level, and turns off the pull-up unit. A holder holds the current gate signal at the voltage level. An inverter turns on/off the holder in response to a first clock signal. A ripple preventer has a source and a gate coupled in common to an output terminal of the pull-up unit and a drain coupled to an input terminal of the inverter, and includes a ripple preventing diode for preventing a ripple from being applied to the inverter.
摘要翻译：一种栅极驱动电路和具有该栅极驱动电路的显示装置，上拉单元在一帧的第一周期期间通过使用第一时钟信号来上拉电流门信号。耦合到上拉单元的上拉驱动器从前一级之一接收进位信号，以接通上拉单元。上拉单元接收来自下一级中的一个的门信号，将当前门信号放电至截止电压电平，并关闭上拉单元。持有者将当前门信号保持在电压电平。逆变器响应于第一个时钟信号打开/关闭支架。波纹防止器具有与上拉单元的输出端子共同耦合的源极和栅极，以及耦合到反相器的输入端子的漏极，并且包括用于防止纹波施加到逆变器的纹波防止二极管。

9. 发明授权

US08164730B2 Liquid crystal display 失效
标题翻译：液晶显示器
公开(公告)号：US08164730B2
公开(公告)日：2012-04-24
申请号：US11511032
申请日：2006-08-28
申请人： Dong-Gyu Kim , Hee-Joon Kim
发明人： Dong-Gyu Kim , Hee-Joon Kim
IPC分类号： G02F1/1343 , G02F1/136
CPC分类号： G02F1/1393 , G02F1/133707 , G02F1/133753 , G02F1/134336 , G02F2001/134345 , G02F2001/134381
摘要： A liquid crystal display includes a substrate and a plurality of pixel electrodes that are formed on the substrate, each of the pixel electrodes including first and second subpixel electrodes, wherein the first and second subpixel electrodes are adjacently disposed in a lateral direction. Each of the first and second subpixel electrodes includes at least two parallelogram shaped electrode pieces having different inclination directions and at least one of electrode pieces of the second subpixel electrode is positioned on or under the first subpixel electrode.
摘要翻译：液晶显示器包括基板和形成在基板上的多个像素电极，每个像素电极包括第一和第二子像素电极，其中第一和第二子像素电极在横向相邻地设置。第一子像素电极和第二子像素电极中的每一个包括具有不同倾斜方向的至少两个平行四边形形状的电极片，并且第二子像素电极的至少一个电极片位于第一子像素电极上或下方。

10. 发明授权

US08040471B2 Liquid crystal display including color filters, and manufacturing method thereof 有权
标题翻译：包括滤色器的液晶显示器及其制造方法
公开(公告)号：US08040471B2
公开(公告)日：2011-10-18
申请号：US12341236
申请日：2008-12-22
申请人： Hee-Joon Kim , Joo-Han Kim , Yeo-Geon Yoon , Jun-Ho Song
发明人： Hee-Joon Kim , Joo-Han Kim , Yeo-Geon Yoon , Jun-Ho Song
IPC分类号： G02F1/1335 , G02F1/1339
CPC分类号： G02F1/13394 , G02F2001/13398 , G02F2001/136222 , G02F2001/136231 , G02F2201/503
摘要： A liquid crystal display includes a first display panel including a first substrate, and first and second color filters disposed on the first substrate and adjacent to each other, a second display panel including a second substrate facing the first display panel and a first spacer disposed on the second substrate, and a liquid crystal layer disposed between the first and second display panels. The first color filter includes a first protrusion protruded toward and overlapped with the second color filter. The first spacer faces the first protrusion, and the first and second display panels contact each other at a location area of the first spacer.
摘要翻译：液晶显示器包括：第一显示面板，包括第一基板;第一和第二滤色器，布置在第一基板上并彼此相邻;第二显示面板，包括面向第一显示面板的第二基板;第一间隔物，第二基板和设置在第一和第二显示面板之间的液晶层。第一滤色器包括向第二滤色器突出并与其重叠的第一突起。第一隔离件面向第一突出部，并且第一和第二显示面板在第一间隔件的位置区域彼此接触。

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