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    • 4. 发明授权
    • Gate driving circuit having improved tolerance to gate voltage ripple and display device having the same
    • 栅极驱动电路具有改善的对栅极电压纹波的容限和具有其的显示器件
    • US08305326B2
    • 2012-11-06
    • US12218814
    • 2008-07-18
    • Sung-Man KimHong-Woo LeeMyung-Koo HurHee-Joon Kim
    • Sung-Man KimHong-Woo LeeMyung-Koo HurHee-Joon Kim
    • G09G3/36
    • G09G3/3677G09G2310/0286G11C19/184
    • A gate driving circuit and a display device having the same, a pull-up unit pulls up a current gate signal by using a first clock signal during a first period of one frame. A pull-up driver coupled to the pull-up unit receives a carry signal from one of the previous stages to turn on the pull-up unit. A pull-up unit receives a gate signal from one of the next stages, discharges the current gate signal to an off voltage level, and turns off the pull-up unit. A holder holds the current gate signal at the voltage level. An inverter turns on/off the holder in response to a first clock signal. A ripple preventer has a source and a gate coupled in common to an output terminal of the pull-up unit and a drain coupled to an input terminal of the inverter, and includes a ripple preventing diode for preventing a ripple from being applied to the inverter.
    • 一种栅极驱动电路和具有该栅极驱动电路的显示装置,上拉单元在一帧的第一周期期间通过使用第一时钟信号来上拉电流门信号。 耦合到上拉单元的上拉驱动器从前一级之一接收进位信号,以接通上拉单元。 上拉单元接收来自下一级中的一个的门信号,将当前门信号放电至截止电压电平,并关闭上拉单元。 持有者将当前门信号保持在电压电平。 逆变器响应于第一个时钟信号打开/关闭支架。 波纹防止器具有与上拉单元的输出端子共同耦合的源极和栅极,以及耦合到反相器的输入端子的漏极,并且包括用于防止纹波施加到逆变器的纹波防止二极管 。
    • 7. 发明授权
    • Touch substrate and method of manufacturing the same
    • 触摸基板及其制造方法
    • US08760419B2
    • 2014-06-24
    • US13028283
    • 2011-02-16
    • Hee-Joon Kim
    • Hee-Joon Kim
    • G06F3/045G06F3/042
    • G06F3/042G06F3/0421Y10T29/49155
    • A touch substrate includes a base substrate, a first sensing element and a first variable voltage part. The first sensing element senses a first light and includes a first active pattern disposed on the base substrate, a first sensing source electrode disposed on the first active pattern, a first sensing drain electrodes disposed on the first active pattern and spaced apart from the first sensing source electrode, and a first sensing gate electrode disposed on the first sensing source electrode and the first sensing drain electrode. The first variable part provides at least one of a first sensing gate voltage and a second sensing gate voltage to the first sensing gate electrode based on reception of the first light, where a level of the second sensing gate voltage is higher than a level of the first sensing gate voltage.
    • 触摸基板包括基底基板,第一感测元件和第一可变电压部件。 第一感测元件感测第一光并且包括设置在基底基板上的第一有源图案,设置在第一有源图案上的第一感测源电极,设置在第一有源图案上并与第一感测元件间隔开的第一感测漏电极 源电极和设置在第一感测源电极和第一感测漏电极上的第一感测栅极电极。 第一可变部件基于第一光的接收向第一感测栅电极提供第一感测栅极电压和第二感测栅极电压中的至少一个,其中第二感测栅极电压的电平高于第一感测栅极电压的电平 第一感测门电压。
    • 10. 发明申请
    • THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF
    • 薄膜晶体管阵列及其制造方法
    • US20090224254A1
    • 2009-09-10
    • US12417280
    • 2009-04-02
    • Je-Hun LEESung-Jin KimHee-Joon KimChang-Oh Jeong
    • Je-Hun LEESung-Jin KimHee-Joon KimChang-Oh Jeong
    • H01L27/06H01L33/00H01L29/786
    • G02F1/13439G02F1/13458H01L27/12H01L27/124H01L29/458H01L29/4908
    • A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn in which the rmetal component is reduced in the IZO, ITO, or a-ITO is not produced on the surfaces of the common electrode.
    • 提供了薄膜晶体管阵列面板,其包括基板,形成在基板上的多个栅极线,在基板上具有透明导电层的多个公共电极,覆盖栅极线和公共电极的栅极绝缘层 形成在所述栅极绝缘层上的多个半导体层,形成在所述半导体层和所述栅极绝缘层上的多个源极电极的多条数据线,形成在所述半导体层上的多个漏电极和所述栅极绝缘体 并且与公共电极重叠并连接到漏电极的多个像素电极。 由于公共电极由ITON,IZON或者-IONON制成,或者是将双重层的ITO / ITON,IZO / IZON或者a-ITO / a-ITON,当注入H 2或SiH 4以形成氮化硅时 SiNX)层,在公共电极的表面上不产生在IZO,ITO或ITO中还原金属成分的不透明金属Sn或Zn。