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1. 发明授权

US07965579B1 Circuit providing load isolation and memory domain translation for memory module 有权
公开(公告)号：US07965579B1
公开(公告)日：2011-06-21
申请号：US12981380
申请日：2010-12-29
申请人： Jeffrey C. Solomon , Jayesh R. Bhakta
发明人： Jeffrey C. Solomon , Jayesh R. Bhakta
IPC分类号： G11C8/00
摘要： A circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of ranks of double-data-rate (DDR) memory devices configured to be activated concurrently with one another in response to a first number of chip-select signals. The circuit is configurable to receive a set of signals comprising address signals and a second number of chip-select signals, the address signals comprising bank address signals. The circuit is further configurable to monitor command signals received by the memory module, to selectively isolate a load of at least one rank of the first number of ranks from the computer system in response to the command signals, and to provide the first number of chip-select signals to the first number of ranks in response at least in part to the received bank address signals and the received second number of chip-select signals.

2. 发明申请

US20110090749A1 CIRCUIT FOR PROVIDING CHIP-SELECT SIGNALS TO A PLURALITY OF RANKS OF A DDR MEMORY MODULE 有权
标题翻译：提供芯片选择信号到DDR存储器模块的多个等级的电路
公开(公告)号：US20110090749A1
公开(公告)日：2011-04-21
申请号：US12954492
申请日：2010-11-24
申请人： Jayesh R. Bhakta , Jeffrey C. Solomon
发明人： Jayesh R. Bhakta , Jeffrey C. Solomon
IPC分类号： G11C8/18 , G11C7/00
CPC分类号： G11C8/12 , G06F12/0207 , G06F12/0215 , G11C5/04 , G11C5/066 , G11C7/1048 , G11C2207/105 , H05K1/181 , H05K2201/10159 , H05K2203/1572 , Y02P70/611
摘要： A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first number of chip-select signals. The circuit is configurable to receive bank address signals, a second number of chip-select signals, and row/column address signals from the computer system. The circuit is further configurable to generate phase-locked clock signals in response to clock signals received from the computer system and to provide the first number of chip-select signals to the first number of ranks in response to the phase-locked clock signals, the received bank address signals, the received second number of chip-select signals, and at least one of the received row/column address signals.
摘要翻译：电路被配置为安装在可连接到计算机系统的存储器模块上，以便电耦合到存储器模块上的多个存储器件。存储器模块具有由第一数量的芯片选择信号激活的第二数量的双数据速率（DDR）存储器件。电路可配置为接收来自计算机系统的存储体地址信号，第二数量的芯片选择信号和行/列地址信号。该电路还可配置为响应于从计算机系统接收的时钟信号而产生锁相时钟信号，并响应于锁相时钟信号将第一数量的芯片选择信号提供给第一数量的等级，接收的存储体地址信号，所接收的第二数量的芯片选择信号，以及所接收的行/列地址信号中的至少一个。

3. 发明授权

US07532537B2 Memory module with a circuit providing load isolation and memory domain translation 有权
公开(公告)号：US07532537B2
公开(公告)日：2009-05-12
申请号：US11335875
申请日：2006-01-19
申请人： Jeffrey C. Solomon , Jayesh R. Bhakta
发明人： Jeffrey C. Solomon , Jayesh R. Bhakta
IPC分类号： G11C8/00
CPC分类号： G11C5/04 , G06F12/0207 , G06F12/0215 , G11C5/066 , G11C7/1048 , G11C8/12 , G11C2207/105 , H05K1/181 , H05K2201/10159 , H05K2203/1572 , Y02D10/13 , Y02P70/611
摘要： A memory module includes a plurality of memory devices and a circuit. Each memory device has a corresponding load. The circuit is electrically coupled to the plurality of memory devices and is configured to be electrically coupled to a memory controller of a computer system. The circuit selectively isolates one or more of the loads of the memory devices from the computer system. The circuit comprises logic which translates between a system memory domain of the computer system and a physical memory domain of the memory module.

4. 发明授权

US08081535B2 Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module 有权
标题翻译：用于向DDR存储器模块的多个等级提供芯片选择信号的电路
公开(公告)号：US08081535B2
公开(公告)日：2011-12-20
申请号：US12954492
申请日：2010-11-24
申请人： Jayesh R. Bhakta , Jeffrey C. Solomon
发明人： Jayesh R. Bhakta , Jeffrey C. Solomon
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G06F12/0207 , G06F12/0215 , G11C5/04 , G11C5/066 , G11C7/1048 , G11C2207/105 , H05K1/181 , H05K2201/10159 , H05K2203/1572 , Y02P70/611
摘要： A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first number of chip-select signals. The circuit is configurable to receive bank address signals, a second number of chip-select signals, and row/column address signals from the computer system. The circuit is further configurable to generate phase-locked clock signals in response to clock signals received from the computer system and to provide the first number of chip-select signals to the first number of ranks in response to the phase-locked clock signals, the received bank address signals, the received second number of chip-select signals, and at least one of the received row/column address signals.
摘要翻译：电路被配置为安装在可连接到计算机系统的存储器模块上，以便电耦合到存储器模块上的多个存储器件。存储器模块具有由第一数量的芯片选择信号激活的第二数量的双数据速率（DDR）存储器件。电路可配置为接收来自计算机系统的存储体地址信号，第二数量的芯片选择信号和行/列地址信号。该电路还可配置为响应于从计算机系统接收的时钟信号而产生锁相时钟信号，并响应于锁相时钟信号将第一数量的芯片选择信号提供给第一数量的等级，接收的存储体地址信号，所接收的第二数量的芯片选择信号，以及所接收的行/列地址信号中的至少一个。

5. 发明授权

US07965578B2 Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module 有权
公开(公告)号：US07965578B2
公开(公告)日：2011-06-21
申请号：US12954492
申请日：2010-11-24
申请人： Jayesh R. Bhakta , Jeffrey C. Solomon
发明人： Jayesh R. Bhakta , Jeffrey C. Solomon
IPC分类号： G11C8/00
摘要： A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first number of chip-select signals. The circuit is configurable to receive bank address signals, a second number of chip-select signals, and row/column address signals from the computer system. The circuit is further configurable to generate phase-locked clock signals in response to clock signals received from the computer system and to provide the first number of chip-select signals to the first number of ranks in response to the phase-locked clock signals, the received bank address signals, the received second number of chip-select signals, and at least one of the received row/column address signals.

6. 发明授权

US07916574B1 Circuit providing load isolation and memory domain translation for memory module 有权
标题翻译：电路为存储器模块提供负载隔离和存储器域转换
公开(公告)号：US07916574B1
公开(公告)日：2011-03-29
申请号：US12955711
申请日：2010-11-29
申请人： Jeffrey C. Solomon , Jayesh R. Bhakta
发明人： Jeffrey C. Solomon , Jayesh R. Bhakta
IPC分类号： G11C8/00
CPC分类号： G06F13/1673 , G06F12/00 , G06F13/00 , G06F13/4243 , G06F13/4282 , G11C5/04 , G11C7/1072 , G11C15/00
摘要： A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first number of chip-select signals. The circuit is configurable to receive bank address signals, a second number of chip-select signals, and row/column address signals from the computer system. The circuit is further configurable to generate phase-locked clock signals in response to clock signals received from the computer system, to selectively isolate one or more loads of the first number of ranks from the computer system, and to translate between a system memory domain and a physical memory domain of the memory module.
摘要翻译：电路被配置为安装在可连接到计算机系统的存储器模块上，以便电耦合到存储器模块上的多个存储器件。存储器模块具有由第一数量的芯片选择信号激活的第二数量的双数据速率（DDR）存储器件。电路可配置为接收来自计算机系统的存储体地址信号，第二数量的芯片选择信号和行/列地址信号。该电路还可配置为响应于从计算机系统接收的时钟信号而产生锁相时钟信号，以便选择性地将计算机系统中的第一数量级别的一个或多个负载隔离，并在系统存储器域和存储器模块的物理内存域。

7. 发明授权

US07864627B2 Memory module decoder 有权
标题翻译：内存模块解码器
公开(公告)号：US07864627B2
公开(公告)日：2011-01-04
申请号：US12577682
申请日：2009-10-12
申请人： Jayesh R. Bhakta , Jeffrey C. Solomon
发明人： Jayesh R. Bhakta , Jeffrey C. Solomon
IPC分类号： G11C8/16
CPC分类号： G11C8/12 , G06F12/0207 , G06F12/0215 , G11C5/04 , G11C5/066 , G11C7/1048 , G11C2207/105 , H05K1/181 , H05K2201/10159 , H05K2203/1572 , Y02P70/611
摘要： A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The plurality of memory devices has a first number of memory devices. The circuit comprises a logic element configurable to receive a set of input signals from the computer system. The circuit further comprising a register and a phase-lock loop circuit, the phase-lock loop circuit configurable to be operatively coupled to the plurality of memory devices, the logic element, and the register. The set of input signals corresponds to a second number of memory devices smaller than the first number of memory devices.
摘要翻译：电路被配置为安装在可连接到计算机系统的存储器模块上，以便电耦合到存储器模块上的多个存储器件。多个存储器件具有第一数量的存储器件。电路包括可配置为从计算机系统接收一组输入信号的逻辑元件。所述电路还包括寄存器和锁相环电路，所述锁相环电路可配置为可操作地耦合到所述多个存储器件，所述逻辑元件和所述寄存器。该组输入信号对应于小于第一数量的存储器件的第二数量的存储器件。

8. 发明申请

US20100091540A1 MEMORY MODULE DECODER 有权
标题翻译：内存模块解码器
公开(公告)号：US20100091540A1
公开(公告)日：2010-04-15
申请号：US12577682
申请日：2009-10-12
申请人： Jayesh R. Bhakta , Jeffrey C. Solomon
发明人： Jayesh R. Bhakta , Jeffrey C. Solomon
IPC分类号： G11C5/02 , G11C8/16 , G11C7/00
CPC分类号： G11C8/12 , G06F12/0207 , G06F12/0215 , G11C5/04 , G11C5/066 , G11C7/1048 , G11C2207/105 , H05K1/181 , H05K2201/10159 , H05K2203/1572 , Y02P70/611
摘要： A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The plurality of memory devices has a first number of memory devices. The circuit comprises a logic element configurable to receive a set of input signals from the computer system. The circuit further comprising a register and a phase-lock loop circuit, the phase-lock loop circuit configurable to be operatively coupled to the plurality of memory devices, the logic element, and the register. The set of input signals corresponds to a second number of memory devices smaller than the first number of memory devices.
摘要翻译：电路被配置为安装在可连接到计算机系统的存储器模块上，以便电耦合到存储器模块上的多个存储器件。多个存储器件具有第一数量的存储器件。电路包括可配置为从计算机系统接收一组输入信号的逻辑元件。所述电路还包括寄存器和锁相环电路，所述锁相环电路可配置为可操作地耦合到所述多个存储器件，所述逻辑元件和所述寄存器。该组输入信号对应于小于第一数量的存储器件的第二数量的存储器件。

9. 发明授权

US08782350B2 Circuit providing load isolation and noise reduction 有权
标题翻译：电路提供负载隔离和降噪
公开(公告)号：US08782350B2
公开(公告)日：2014-07-15
申请号：US13412243
申请日：2012-03-05
申请人： Hyun Lee , Jayesh R. Bhakta , Jeffrey C. Solomon , Mario Jesus Martinez , Chi-She Chen
发明人： Hyun Lee , Jayesh R. Bhakta , Jeffrey C. Solomon , Mario Jesus Martinez , Chi-She Chen
IPC分类号： G06F12/00 , H05K1/02
CPC分类号： G06F13/1684 , G06F13/4027 , G11C5/02 , G11C5/06 , G11C8/18 , H05K1/0216 , H05K1/0243 , H05K2201/10053 , H05K2201/10159 , H05K2201/10189
摘要： Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.
摘要翻译：本文描述的某些实施例包括具有印刷电路板的存储器模块，该印刷电路板包括被配置为可操作地耦合到计算机系统的存储器控制器的至少一个连接器。存储器模块还包括印刷电路板上的多个存储器件和包括可操作地耦合到至少一个存储器件的第一组端口的电路。电路还包括可操作地耦合到至少一个连接器的第二组端口。电路包括切换电路，其被配置为选择性地将第二组端口的一个或多个端口耦合到第一组端口的一个或多个端口。第一组和第二组的每个端口包括校正电路，其减少在第一组端口和第二组端口之间传输的一个或多个信号中的噪声。

10. 发明授权

US08081536B1 Circuit for memory module 有权
标题翻译：内存模块电路
公开(公告)号：US08081536B1
公开(公告)日：2011-12-20
申请号：US13032470
申请日：2011-02-22
申请人： Jeffrey C. Solomon , Jayesh R. Bhakta
发明人： Jeffrey C. Solomon , Jayesh R. Bhakta
IPC分类号： G11C8/00
CPC分类号： G06F13/1673 , G06F12/00 , G06F13/00 , G06F13/4243 , G06F13/4282 , G11C5/04 , G11C7/1072 , G11C15/00
摘要： A circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of ranks of double-data-rate (DDR) memory circuits activated by a first number of chip-select signals. The circuit is configurable to receive a set of signals comprising address signals and a second number of chip-select signals smaller than the first number of chip-select signals. The circuit is further configurable to generate phase-locked clock signals, to selectively isolate a load of at least one rank of the first number of ranks from the computer system in response at least in part to the set of signals, and to generate the first number of chip-select signals in response at least in part to the phase-locked clock signals, the address signals, and the second number of chip-select signals.
摘要翻译：电路被配置为安装在被配置为可操作地耦合到计算机系统的存储器模块上。存储器模块具有由第一数量的芯片选择信号激活的第一数量的双数据速率（DDR）存储器电路。电路可配置为接收包括地址信号和小于第一数量的芯片选择信号的第二数量的芯片选择信号的信号。该电路还可配置成产生锁相时钟信号，以至少部分地响应于该组信号来选择性地隔离来自计算机系统的第一数量级别的至少一级的负载，并且产生第一芯片选择信号的数量至少部分地响应于锁相时钟信号，地址信号和第二数量的芯片选择信号。

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