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1. 发明授权

US5947053A Wear-through detector for multilayered parts and methods of using same 失效
标题翻译：用于多层零件的磨损检测器及其使用方法
公开(公告)号：US5947053A
公开(公告)日：1999-09-07
申请号：US5634
申请日：1998-01-09
申请人： Jay Burnham , Harold G. Linde , Nicholas N. Mone, Jr. , Ronald A. Warren
发明人： Jay Burnham , Harold G. Linde , Nicholas N. Mone, Jr. , Ronald A. Warren
IPC分类号： G01N17/00 , G01B15/00 , G01B21/08 , G21K5/04 , G21K5/08
CPC分类号： G01N17/00 , H01J2237/30466 , H01J2237/31701
摘要： The present invention relates to wear-through detection in multilayered parts. This invention specifically encompasses, in one aspect, wear-through detection in semiconductor vacuum processing systems in which a wear indicator that will release a detectable constituent upon exposure to processing conditions is used inside the semiconductor vacuum processing tool. This invention permits real time detection of wear during operation of semiconductor vacuum processing equipment.
摘要翻译：本发明涉及多层部件中的磨损检测。本发明在一个方面具体包括半导体真空处理系统中的穿透检测，其中在半导体真空处理工具内部使用将在暴露于加工条件时释放可检测成分的磨损指示器。本发明允许在半导体真空处理设备的操作期间实时检测磨损。

2. 发明授权

US5539080A Polyimide and a semiconductor prepared therefrom 失效
标题翻译：聚酰亚胺和由其制备的半导体
公开(公告)号：US5539080A
公开(公告)日：1996-07-23
申请号：US424986
申请日：1995-04-19
申请人： Dennis P. Hogan , Harold G. Linde , Ronald A. Warren
发明人： Dennis P. Hogan , Harold G. Linde , Ronald A. Warren
IPC分类号： C08G73/10 , C08K5/3437 , C08L77/00 , C08L79/08 , G03F7/09 , G03F7/11 , H01L21/027
CPC分类号： G03F7/091 , Y10S428/901 , Y10S430/11 , Y10T428/24917 , Y10T428/31692 , Y10T428/31721
摘要： A process is disclosed for making circuit elements by photolithography comprising depositing an antireflective polyimide or polyimide precursor layer on a substrate and heating the substrate at 200.degree. C. to 500.degree. to provide a functional integrated circuit element that includes an antireflective polyimide layer. The antireflective polyimide layer contains a sufficient concentration of at least one chromophore to give rise to an absorbance sufficient to attenuate actinic radiation at 405 or 436 nm. Preferred chromophores include those arising from perylenes, naphthalenes and anthraquinones. The chromophore may reside in a dye which is a component of the polyimide coating mixture or it may reside in a residue which is incorporated into the polyimide itself.
摘要翻译：公开了一种用于通过光刻制造电路元件的方法，包括在衬底上沉积抗反射聚酰亚胺或聚酰亚胺前体层并在200℃至500℃下加热衬底以提供包括抗反射聚酰亚胺层的功能集成电路元件。抗反射聚酰亚胺层含有足够浓度的至少一种发色团，以产生足够的吸光度，以减弱405或436nm处的光化辐射。优选的发色团包括由苝，萘和蒽醌衍生的那些。发色团可以存在于作为聚酰亚胺涂料混合物的组分的染料中，或者可以存在于聚酰亚胺本身中的残余物中。

3. 发明授权

US5397684A Antireflective polyimide dielectric for photolithography 失效
标题翻译：用于光刻的抗反射聚酰亚胺电介质
公开(公告)号：US5397684A
公开(公告)日：1995-03-14
申请号：US54500
申请日：1993-04-27
申请人： Dennis P. Hogan , Harold G. Linde , Ronald A. Warren
发明人： Dennis P. Hogan , Harold G. Linde , Ronald A. Warren
IPC分类号： C08G73/10 , C08K5/3437 , C08L77/00 , C08L79/08 , G03F7/09 , G03F7/11 , H01L21/027 , G03C5/00
CPC分类号： G03F7/091 , Y10S428/901 , Y10S430/11 , Y10T428/24917 , Y10T428/31692 , Y10T428/31721
摘要： A process is disclosed for making circuit elements by photolithography comprising depositing an antireflective polyimide or polyimide precursor layer on a substrate and heating the substrate at 200.degree. C. to 500.degree. to provide a functional integrated circuit element that includes an antireflective polyimide layer. The antireflective polyimide layer contains a sufficient concentration of at least one chromophore to give rise to an absorbance sufficient to attenuate actinic radiation at 405 or 436 nm. Preferred chromophores include those arising from perylenes, naphthalenes and anthraquinones. The chromophore may reside in a dye which is a component of the polyimide coating mixture or it may reside in a residue which is incorporated into the polyimide itself.
摘要翻译：公开了一种用于通过光刻制造电路元件的方法，包括在衬底上沉积抗反射聚酰亚胺或聚酰亚胺前体层并在200℃至500℃下加热衬底以提供包括抗反射聚酰亚胺层的功能集成电路元件。抗反射聚酰亚胺层含有足够浓度的至少一种发色团，以产生足够的吸光度，以减弱405或436nm处的光化辐射。优选的发色团包括由苝，萘和蒽醌衍生的那些。发色团可以存在于作为聚酰亚胺涂料混合物的组分的染料中，或者可以存在于聚酰亚胺本身中的残余物中。

4. 发明授权

US5441797A Antireflective polyimide dielectric for photolithography 失效
标题翻译：用于光刻的抗反射聚酰亚胺电介质
公开(公告)号：US5441797A
公开(公告)日：1995-08-15
申请号：US315801
申请日：1994-09-30
申请人： Dennis P. Hogan , Harold G. Linde , Ronald A. Warren
发明人： Dennis P. Hogan , Harold G. Linde , Ronald A. Warren
IPC分类号： C08G73/10 , C08K5/3437 , C08L77/00 , C08L79/08 , G03F7/09 , G03F7/11 , H01L21/027 , B32B9/00
CPC分类号： G03F7/091 , Y10S428/901 , Y10S430/11 , Y10T428/24917 , Y10T428/31692 , Y10T428/31721
摘要： A process is disclosed for making circuit elements by photolithography comprising depositing an antireflective polyimide or polyimide precursor layer on a substrate and heating the substrate at 200.degree. C. to 500.degree. C. to provide a functional integrated circuit element that includes an antireflective polyimide layer. The antireflective polyimide layer contains a sufficient concentration of at least one chromophore to give rise to an absorbance sufficient to attenuate actinic radiation at 405 or 436 nm. Preferred chromophores include those arising from perylenes, naphthalenes and anthraquinones. The chromophore may reside in a dye which is a component of the polyimide coating mixture or it may reside in a residue which is incorporated into the polyimide itself.
摘要翻译：公开了一种用于通过光刻制造电路元件的方法，包括在衬底上沉积抗反射聚酰亚胺或聚酰亚胺前体层并在200℃至500℃下加热衬底以提供包括抗反射聚酰亚胺层的功能集成电路元件。抗反射聚酰亚胺层含有足够浓度的至少一种发色团，以产生足够的吸光度，以减弱405或436nm处的光化辐射。优选的发色团包括由苝，萘和蒽醌衍生的那些。发色团可以存在于作为聚酰亚胺涂料混合物的组分的染料中，或者可以存在于聚酰亚胺本身中的残余物中。

5. 发明授权

US5536792A Antireflective polymide dielectric for photolithography 失效
标题翻译：空值
公开(公告)号：US5536792A
公开(公告)日：1996-07-16
申请号：US423478
申请日：1995-04-19
申请人： Dennis P. Hogan , Harold G. Linde , Ronald A. Warren
发明人： Dennis P. Hogan , Harold G. Linde , Ronald A. Warren
IPC分类号： C08G73/10 , C08K5/3437 , C08L77/00 , C08L79/08 , G03F7/09 , G03F7/11 , H01L21/027
CPC分类号： G03F7/091 , Y10S428/901 , Y10S430/11 , Y10T428/24917 , Y10T428/31692 , Y10T428/31721
摘要： A process is disclosed for making circuit elements by photolithography comprising depositing an antireflective polyimide or polyimide precursor layer on a substrate and heating the substrate at 200.degree. C. to 500.degree. to provide a functional integrated circuit element that includes an antireflective polyimide layer. The antireflective polyimide layer contains a sufficient concentration of at least one chromophore to give rise to an absorbance sufficient to attenuate actinic radiation at 405 or 436 nm. Preferred chromophores include those arising from perylenes, naphthalenes and anthraquinones. The chromophore may reside in a dye which is a component of the polyimide coating mixture or it may reside in a residue which is incorporated into the polyimide itself.
摘要翻译：公开了一种用于通过光刻制造电路元件的方法，包括在衬底上沉积抗反射聚酰亚胺或聚酰亚胺前体层并在200℃至500℃下加热衬底以提供包括抗反射聚酰亚胺层的功能集成电路元件。抗反射聚酰亚胺层含有足够浓度的至少一种发色团，以产生足够的吸光度，以减弱405或436nm处的光化辐射。优选的发色团包括由苝，萘和蒽醌衍生的那些。发色团可以存在于作为聚酰亚胺涂料混合物的组分的染料中，或者可以存在于聚酰亚胺本身中的残余物中。

6. 发明授权

US07332054B2 Etch apparatus 有权
标题翻译：蚀刻装置
公开(公告)号：US07332054B2
公开(公告)日：2008-02-19
申请号：US10760896
申请日：2004-01-20
申请人： Arne W. Ballantine , Scott A. Estes , Emily E. Fisch , Gary Milo , Ronald A. Warren
发明人： Arne W. Ballantine , Scott A. Estes , Emily E. Fisch , Gary Milo , Ronald A. Warren
IPC分类号： H01L21/00 , B05C3/00 , B05D45/00
CPC分类号： H01L21/67086 , H01L21/31111 , H01L21/32134 , Y10S134/902
摘要： In a process using a hot phosphoric acid etchant (12) to etch silicon nitride on a semiconductor wafer (15) submerged in a tank (11) of the etchant (12), a recirculating path is established for the etchant (12). A porous filter (35) is coated with silicon nitride and installed in the recirculating path. As the etchant (12) in the recirculating path flows through the porous filter (35), the silicon nitride on the porous filter (35) dissolves into the etchant (12). In the tank (11), the silicon nitride dissolved in the etchant (12) significantly suppresses the etch of silicon dioxide on the semiconductor wafer (15), thereby enhancing the etch selectivity of the process. Monitoring and maintaining the concentration of the silicon nitride in the etchant (12) stabilizes the etch selectivity of the process.
摘要翻译：在使用热磷酸蚀刻剂（12）蚀刻浸没在蚀刻剂（12）的罐（11）中的半导体晶片（15）上的氮化硅的方法中，为蚀刻剂（12）建立再循环路径。多孔过滤器（35）涂覆有氮化硅并且安装在再循环路径中。当再循环路径中的蚀刻剂（12）流过多孔过滤器（35）时，多孔过滤器（35）上的氮化硅溶解到蚀刻剂（12）中。在罐（11）中，溶解在蚀刻剂（12）中的氮化硅显着地抑制了半导体晶片（15）上的二氧化硅的蚀刻，从而提高了工艺的蚀刻选择性。监测和维持蚀刻剂（12）中氮化硅的浓度稳定了工艺的蚀刻选择性。

7. 发明授权

US5982225A Hot electron compensation for improved MOS transistor reliability 失效
标题翻译：热电子补偿提高了MOS晶体管的可靠性
公开(公告)号：US5982225A
公开(公告)日：1999-11-09
申请号：US907149
申请日：1997-08-06
申请人： Timothy E. Forhan , Terence B. Hook , Steven W. Mittl , Edward J. Nowak , Madhu Sayala , Ronald A. Warren
发明人： Timothy E. Forhan , Terence B. Hook , Steven W. Mittl , Edward J. Nowak , Madhu Sayala , Ronald A. Warren
IPC分类号： H03K17/10 , H03K17/14 , H03K17/06 , H03K17/687
CPC分类号： H03K17/102 , H03K17/145
摘要： A circuit actively monitors and measures the amount of MOS device degradation due to, for example, the hot electron effect, and makes compensatory adjustments to device voltage levels or clock speed to maintain desired levels of functionality and performance. Monitoring can be done separately for NFET and PFET devices to selectively adjust for different degradation rates between the two. In operation, the monitor circuit compares the performance of a stressed device to a reference device, that is, an unstressed device which has not been degraded by the hot-electron effect. The monitor circuit outputs a signal indicating the amount of device degradation. This signal is used to adjust the supply voltage to that device or to the chip or otherwise compensate for the degradation. The monitor circuit can be formed on-chip or off-chip.
摘要翻译：电路主动监测和测量由于例如热电子效应引起的MOS器件退化的量，并且对器件电压电平或时钟速度进行补偿性调整以维持期望的功能和性能水平。可以分别对NFET和PFET器件进行监控，以选择性地调整两者之间的不同降解率。在操作中，监视电路将应力装置的性能与参考装置进行比较，即，未受热电子效应劣化的未受应力的装置。监视电路输出指示设备劣化量的信号。该信号用于调整该器件或芯片的电源电压或以其他方式补偿降级。监控电路可以片上或片外形成。

8. 发明授权

US5427622A Method for uniform cleaning of wafers using megasonic energy 失效
标题翻译：使用兆声波能量均匀清洁晶片的方法
公开(公告)号：US5427622A
公开(公告)日：1995-06-27
申请号：US276684
申请日：1994-07-18
申请人： David Stanasolovich , William A. Syverson , Ronald A. Warren
发明人： David Stanasolovich , William A. Syverson , Ronald A. Warren
IPC分类号： E04B1/84 , H01L21/00 , B08B3/12
CPC分类号： H01L21/67057 , E04B2001/8419 , Y10S134/902
摘要： Apparatus and method for cleaning/etching the surface of an article with sonic energy in the megahertz range which employ an anti-reflection mechanism within a recirculation tank. A tank having at least one side wall and a bottom structure holds a cleaning/etching liquid and a megasonic transducer is associated with the tank for projecting megasonic energy into the liquid. The anti-reflection mechanism is disposed within the tank in close association with the at least one sidewall or bottom structure of the tank to thereby minimize reflection of megasonic energy from the associated surface. Preferably, the megasonic transducer is associated with a first tank sidewall which opposes a second tank sidewall, and the anti-reflection mechanism is disposed adjacent the second tank sidewall. By way of example, the anti-reflection mechanism can comprise a stream of gas bubbles, a plurality of anechoic structures, or a combination of both gas bubbles and anechoic structures.
摘要翻译：用于在兆赫兹范围内用声能量清洁/蚀刻物品的表面的装置和方法，其在循环罐内采用防反射机构。具有至少一个侧壁和底部结构的罐保持清洁/蚀刻液体，并且兆声波换能器与用于将兆声波能量投射到液体中的罐相关联。防反射机构设置在罐内与罐的至少一个侧壁或底部结构紧密相关联，从而最小化来自相关联表面的兆声波能量的反射。优选地，兆声波换能器与第二坦克侧壁相对，第一坦克侧壁与第二坦克侧壁相对，并且防反射机构邻近第二坦克侧壁设置。作为示例，防反射机构可以包括气泡流，多个消声结构或两个气泡和消声结构的组合。

9. 发明授权

US5216282A Self-aligned contact studs for semiconductor structures 失效
标题翻译：用于半导体结构的自对准接触器
公开(公告)号：US5216282A
公开(公告)日：1993-06-01
申请号：US784193
申请日：1991-10-29
申请人： Donna R. Cote , David Stanasolovich , Ronald A. Warren
发明人： Donna R. Cote , David Stanasolovich , Ronald A. Warren
IPC分类号： H01L21/28 , H01L21/3105 , H01L21/336 , H01L21/60 , H01L21/768 , H01L23/48 , H01L23/522 , H01L29/78
CPC分类号： H01L23/5226 , H01L21/3105 , H01L21/76877 , H01L21/76879 , H01L21/76897 , H01L2924/0002
摘要： A contact stud for a semiconductor structure is fabricated by providing a semiconductor substrate having an alignment structure, which includes a sidewall, and the semiconductor structure formed thereon, forming a sidewall spacer contiguous with the semiconductor structure and the sidewall of the alignment structure, depositing an insulating layer contiguous with the sidewall spacer so as to insulate the semiconductor structure, etching the sidewall spacer selectively to the sidewall of the alignment structure, the semiconductor structure and the insulating layer for forming a contact window opening for allowing access to the semiconductor structure, and backfilling the contact window opening with a conductive material so as to contact the semiconductor structure for forming the stud.

10. 发明授权

US5187121A Process for fabrication of a semiconductor structure and contact stud 失效
标题翻译：用于制造半导体结构和接触柱的方法
公开(公告)号：US5187121A
公开(公告)日：1993-02-16
申请号：US810004
申请日：1991-12-18
申请人： Donna R. Cote , David Stanasolovich , Ronald A. Warren
发明人： Donna R. Cote , David Stanasolovich , Ronald A. Warren
IPC分类号： H01L21/28 , H01L21/3105 , H01L21/311 , H01L21/318 , H01L21/768
CPC分类号： H01L21/76802 , H01L21/31051 , H01L21/31116 , H01L21/318 , H01L21/76885
摘要： Self-aligning process for fabricating a semiconductor structure and stud therefor on a semiconductor substrate comprises depositing a first material onto the substrate, depositing a second material onto the first material, removing excess portions of second material so as to form openings through the second material exposing excess portions of first material, whereby a selected portion of second material is retained and forms a sacrificial element, removing the excess portions of first material selectively to the substrate so as to extend the openings through the first material to the substrate, whereby a selected portion of first material is retained and forms the semiconductor structure, filling the openings with an insulating material, removing the sacrificial element selectively to the insulating material and the semiconductor structure for forming a contact window opening for allowing access to the semiconductor structure, and filling the contact window opening with stud material so as to contact the semiconductor structure for forming the stud.
摘要翻译：用于在半导体衬底上制造半导体结构和螺柱的自对准工艺包括将第一材料沉积到衬底上，将第二材料沉积到第一材料上，去除第二材料的多余部分，以便通过第二材料暴露第一材料的多余部分，由此保留第二材料的选定部分并形成牺牲元件，将第一材料的多余部分选择性地去除到衬底上，以将开口延伸穿过第一材料到衬底，由此选择部分的第一材料被保持并形成半导体结构，用绝缘材料填充开口，将牺牲元件选择性地去除绝缘材料和用于形成用于允许接近半导体结构的接触窗口的半导体结构，并且填充接触窗口打开与螺柱材料从而与形成螺柱的半导体结构接触。

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