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1. 发明申请

US20050138474A1 Circuit verification using multiple engines 失效
标题翻译：使用多台发动机进行电路验证
公开(公告)号：US20050138474A1
公开(公告)日：2005-06-23
申请号：US10996706
申请日：2004-11-22
申请人： Jawahar Jain , Koichiro Takayama , Debashis Sahoo
发明人： Jawahar Jain , Koichiro Takayama , Debashis Sahoo
IPC分类号： G06F17/50 , F28F7/00 , G06F11/00 , H03M13/03
CPC分类号： G01R31/31703 , G01R31/318342
摘要： In one embodiment, a method for circuit verification using multiple engines includes running multiple traces on a circuit using multiple reachability algorithms, selecting an effective reachability algorithm for the circuit from among the multiple reachability algorithms according to a comparison of results of the multiple traces with each other, generating a set of initial states for the selected effective reachability algorithm using states reached in the plurality of traces, and executing the selected effective reachability algorithm using the generated set of initial states to verify the circuit.
摘要翻译：在一个实施例中，使用多个引擎的电路验证的方法包括使用多个可达性算法在电路上运行多条迹线，根据多条迹线与每条迹线的结果的比较，从多个可达性算法中选择用于该电路的有效可达性算法另一方面，使用在所述多个迹线中达到的状态产生所述选择的有效可达性算法的一组初始状态，以及使用所生成的初始状态集来执行所选择的有效可达性算法以验证所述电路。

2. 发明授权

US07281225B2 Circuit verification using multiple engines 失效
标题翻译：使用多台发动机的电路验证
公开(公告)号：US07281225B2
公开(公告)日：2007-10-09
申请号：US10996706
申请日：2004-11-22
申请人： Jawahar Jain , Koichiro Takayama , Debashis Sahoo
发明人： Jawahar Jain , Koichiro Takayama , Debashis Sahoo
IPC分类号： G06F17/50
CPC分类号： G01R31/31703 , G01R31/318342
摘要： In one embodiment, a method for circuit verification using multiple engines includes running multiple traces on a circuit using multiple reachability algorithms, selecting an effective reachability algorithm for the circuit from among the multiple reachability algorithms according to a comparison of results of the multiple traces with each other, generating a set of initial states for the selected effective reachability algorithm using states reached in the plurality of traces, and executing the selected effective reachability algorithm using the generated set of initial states to verify the circuit.
摘要翻译：在一个实施例中，使用多个引擎的电路验证的方法包括使用多个可达性算法在电路上运行多条迹线，根据多条迹线与每条迹线的结果的比较，从多个可达性算法中选择用于该电路的有效可达性算法另一方面，使用在所述多个迹线中达到的状态产生所述选择的有效可达性算法的一组初始状态，以及使用所生成的初始状态集来执行所选择的有效可达性算法以验证所述电路。

3. 发明授权

US06301687B1 Method for verification of combinational circuits using a filtering oriented approach 有权
标题翻译：使用基于过滤的方法验证组合电路的方法
公开(公告)号：US06301687B1
公开(公告)日：2001-10-09
申请号：US09556038
申请日：2000-04-20
申请人： Jawahar Jain , Rajarshi Mukherjee , Koichiro Takayama
发明人： Jawahar Jain , Rajarshi Mukherjee , Koichiro Takayama
IPC分类号： G06F1750
CPC分类号： G01R31/318357 , G01R31/318371 , G01R31/318385 , G06F17/504
摘要： A set of filters are arranged in sequence for verification and analysis of digital circuit designs. The filters are either active filters, which are directly involved in verification of circuit designs (e.g., a Binary Decision Diagram (BDD)-based verifier or an automatic test pattern generation (ATPG)-based verifier), or passive filters, which gather information about the circuit or transform the circuit structure in order to simplify the verification problem (e.g., random pattern simulation or circuit partitioning). Given a pair of circuits to be verified, the filter approach first subjects the circuits to very simple, fast techniques having very low memory usage requirements. These steps are followed by a series of increasingly powerful methods that are more time consuming and often require more computer memory for their operation. In between the simpler active filters and the more sophisticated active filters, information about potential equivalent nodes in the circuits is collected and a decision is made as to whether to partition the circuits. The verification methodology is structured such that circuit designs that are easier to verify are never unnecessarily subjected to more expensive techniques. The method provides for a gradual increase in the sophistication of verification techniques applied, according to the difficulty of the verification problem.
摘要翻译：一组滤波器按顺序排列，用于数字电路设计的验证和分析。滤波器是有源滤波器，其直接涉及电路设计的验证（例如，基于二进制决策图（BDD）的验证器或基于自动测试模式生成（ATPG）的验证器）或无源滤波器，其收集信息关于电路或转换电路结构，以简化验证问题（例如，随机模式仿真或电路划分）。给定要验证的一对电路，滤波器方法首先使电路以非常简单，快速的技术使用，具有非常低的存储器使用要求。这些步骤之后是一系列日益强大的方法，这些方法更耗时，并且通常需要更多的计算机内存来进行操作。在更简单的有源滤波器和更复杂的有源滤波器之间，收集关于电路中的潜在等效节点的信息，并且决定是否划分电路。验证方法被构造成使得更容易验证的电路设计不会不必要地经受更昂贵的技术。该方法根据验证问题的难度逐渐提高了应用验证技术的复杂性。

4. 发明授权

US6086626A Method for verification of combinational circuits using a filtering oriented approach 失效
标题翻译：使用基于过滤的方法验证组合电路的方法
公开(公告)号：US6086626A
公开(公告)日：2000-07-11
申请号：US857916
申请日：1997-05-16
申请人： Jawahar Jain , Rajarshi Mukherjee , Koichiro Takayama
发明人： Jawahar Jain , Rajarshi Mukherjee , Koichiro Takayama
IPC分类号： G01R31/28 , G01R31/3183 , G06F17/50 , G06F19/00 , G06Q50/00 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G01R31/318357 , G01R31/318371 , G01R31/318385 , G06F17/504
摘要： A set of filters are arranged in sequence for verification and analysis of digital circuit designs. The filters are either active filters, which are directly involved in verification of circuit designs (e.g., a Binary Decision Diagram (BDD)-based verifier or an automatic test pattern generation (ATPG)-based verifier), or passive filters, which gather information about the circuit or transform the circuit structure in order to simplify the verification problem (e.g., random pattern simulation or circuit partitioning). Given a pair of circuits to be verified, the filter approach first subjects the circuits to very simple, fast techniques having very low memory usage requirements. These steps are followed by a series of increasingly powerful methods that are more time consuming and often require more computer memory for their operation. In between the simpler active filters and the more sophisticated active filters, information about potential equivalent nodes in the circuits is collected and a decision is made as to whether to partition the circuits. The verification methodology is structured such that circuit designs that are easier to verify are never unnecessarily subjected to more expensive techniques. The method provides for a gradual increase in the sophistication of verification techniques applied, according to the difficulty of the verification problem.
摘要翻译：一组滤波器按顺序排列，用于数字电路设计的验证和分析。该过滤器是任一有源滤波器，它直接参与在电路设计中的验证（例如，二元决策图（BDD）系验证或自动测试模式产生（ATPG）系检验器），或无源滤波器，其中收集信息关于电路或转换电路结构，以简化验证问题（例如，随机模式仿真或电路划分）。给定要验证的一对电路，滤波器方法首先使电路以非常简单，快速的技术使用，具有非常低的存储器使用要求。这些步骤之后是一系列日益强大的方法，这些方法更耗时，并且通常需要更多的计算机内存来进行操作。在更简单的有源滤波器和更复杂的有源滤波器之间，收集关于电路中的潜在等效节点的信息，并且决定是否划分电路。验证方法被构造成使得更容易验证的电路设计不会不必要地经受更昂贵的技术。该方法根据验证问题的难度逐渐提高了应用验证技术的复杂性。

5. 发明授权

US08079003B2 Verification support apparatus, verification support method, and computer product 有权
标题翻译：验证支持设备，验证支持方法和计算机产品
公开(公告)号：US08079003B2
公开(公告)日：2011-12-13
申请号：US12353868
申请日：2009-01-14
申请人： Koichiro Takayama
发明人： Koichiro Takayama
IPC分类号： G06F9/455
CPC分类号： G06F17/5022
摘要： In a verification support apparatus, an implementation description of a verification target is acquired and based on the implementation description, a combination of input gates is identified. A pair of output cones including gates to which input signals from the input gates reach, and a common output cone including gates common to the pair of output cones, are detected. Based on the common output cone, a degree of relation between the input gates is calculated and according to the calculation, the strength of relation is determined for the combination of input gates. The strength of relation for a combination of the input gates is set, the combination being based on a specification of the verification target and corresponding to the combination identified from the implementation description. Whether the strength of relation set and that determined for the identified combination coincide is judged and a result of the judgment is output.
摘要翻译：在验证支持装置中，获取验证对象的实现描述，并且基于实现描述，识别输入门的组合。检测包括输入门的输入信号到达门的一对输出锥，以及包括一对输出锥公共的共用输出锥。基于公共输出锥，计算输入门之间的关系度，根据计算，确定输入门组合的关系强度。设置输入门组合的关系强度，该组合基于验证对象的指定并对应于从实现描述识别的组合。判断关系集合的强度和确定的组合的强度是否一致，并且输出判断结果。

6. 发明授权

US07984403B2 Verification supporting system 有权
标题翻译：验证支持系统
公开(公告)号：US07984403B2
公开(公告)日：2011-07-19
申请号：US12359105
申请日：2009-01-23
申请人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
发明人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/504
摘要： A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.
摘要翻译：从验证目标电路的配置指定要验证的验证目标寄存器，并且提取需要验证的模式作为关于指定验证目标寄存器的覆盖标准。当提取模式时，准备一个DIRW矩阵，以指示包含在验证目标电路中的寄存器中的四个状态中声明，初始化，读取和写入中的可能发生的状态转换，并用于确定两个覆盖标准，矩阵覆盖标准和实施覆盖标准。

7. 发明申请

US20080312890A1 SPECIFICATION VERIFICATION PROGRAM, COMPUTER-READABLE STORAGE MEDIUM STORING SPECIFICATION VERIFICATION PROGRAM, SPECIFICATION VERIFICATION APPARATUS, AND SPECIFICATION VERIFICATION METHOD 有权
标题翻译：规格验证程序，计算机可读存储介质存储规范验证程序，规范验证设备和规范验证方法
公开(公告)号：US20080312890A1
公开(公告)日：2008-12-18
申请号：US12136378
申请日：2008-06-10
申请人： Qiang ZHU , Hiroaki Iwashita , Koichiro Takayama , Tsuneo Nakata
发明人： Qiang ZHU , Hiroaki Iwashita , Koichiro Takayama , Tsuneo Nakata
IPC分类号： G06G7/48
CPC分类号： G06F8/10
摘要： Conditions necessary to be satisfied for execution of each use case from a use case description indicative of a requirements specification of the design object are acquired. Then a state satisfying the conditions, from among a set of states represented in a finite state machine model indicative of a design specification of the design object are detected. A presence or absence of an undetected state in the set of states in accordance with the detection is determined and output.
摘要翻译：获取从指示设计对象的要求规范的用例描述中执行每个用例所需要的条件。然后，检测从表示设计对象的设计规格的有限状态机模型中表示的一组状态中满足条件的状态。确定并输出根据检测的状态集合中的未检测状态的存在或不存在。

8. 发明授权

US07168014B2 Propagating an error through a network 失效
标题翻译：通过网络传播错误
公开(公告)号：US07168014B2
公开(公告)日：2007-01-23
申请号：US10405766
申请日：2003-04-01
申请人： Indradeep Ghosh , Koichiro Takayama , Liang Zhang
发明人： Indradeep Ghosh , Koichiro Takayama , Liang Zhang
IPC分类号： G01R31/28
CPC分类号： G01R31/318342
摘要： Propagating an error through a network includes receiving a network having propagation paths and nodes, where a propagation path has one or more nodes and a node is associated with a variable operable to have a value during simulation. A tag of a tag set is assigned to the value. The tag set includes at least two signed tags, positive tag representing a positive error and a negative tag representing a negative error, and an unsigned tag representing an error having an unknown sign. The tag is propagated along the propagation path to yield intermediate tags, where at least one intermediate tag is an unsigned tag formed from at least two signed tags. A final tag is determined in accordance with the intermediate tags in order to propagate an error through the network.
摘要翻译：通过网络传播错误包括接收具有传播路径和节点的网络，其中传播路径具有一个或多个节点，并且节点与可操作以在仿真期间具有值的变量相关联。标签集的标签被分配给该值。标签集包括至少两个签名的标签，表示正错误的正标签和表示负错误的负标签，以及表示具有未知符号的错误的无符号标签。标签沿着传播路径传播以产生中间标签，其中至少一个中间标签是由至少两个签名的标签形成的无符号标签。根据中间标签确定最终标签，以便通过网络传播错误。

9. 发明授权

US06334156B1 Node grouping method and data transmitting method in a network 失效
标题翻译：网络中的节点分组方法和数据传输方法
公开(公告)号：US06334156B1
公开(公告)日：2001-12-25
申请号：US08531204
申请日：1995-09-19
申请人： Hidetoshi Matsuoka , Fumiyasu Hirose , Shintaro Shimogori , Koichiro Takayama
发明人： Hidetoshi Matsuoka , Fumiyasu Hirose , Shintaro Shimogori , Koichiro Takayama
IPC分类号： G06F1516
CPC分类号： H04L45/04
摘要： All nodes in a network are classified into hierarchical groups. Each node belongs to any group in all hierarchical groups from the highest order group to the lowest order group. The node is assigned a hierarchical address corresponding to each hierarchical group. Thus, the amount of routing information required for data transfer can be reduced, thereby efficiently transmitting data.
摘要翻译：网络中的所有节点都分为层次组。每个节点属于从最高订单组到最低订单组的所有分层组中的任何组。为每个分层组分配一个分层地址。因此，可以减少数据传输所需的路由信息量，从而有效地发送数据。

10. 发明申请

US20110138228A1 VERIFICATION COMPUTER PRODUCT AND APPARATUS 审中-公开
标题翻译：验证计算机产品和设备
公开(公告)号：US20110138228A1
公开(公告)日：2011-06-09
申请号：US12957970
申请日：2010-12-01
申请人： Koichiro Takayama , Rafael Kazumiti Morizawa
发明人： Koichiro Takayama , Rafael Kazumiti Morizawa
IPC分类号： G06F11/22
CPC分类号： G06F11/263
摘要： A non-transitory, computer-readable recording medium stores therein a verification program that causes a computer to execute detecting from a structure expressing a group of scenarios for verifying an operation of a design under verification and by hierarchizing sequences for realizing the operation as nodes, a similar node similar to a faulty node representing a sequence in which a fault has occurred; generating a string of sequences represented by a group of nodes on a path starting from a start node of the structure to the detected similar node; and outputting the generated string of sequences.
摘要翻译：一种非暂时的计算机可读记录介质，其中存储有使计算机从表示一组场景的结构执行检测的验证程序，用于验证正在验证的设计的操作，并且通过将用于实现作为节点的操作的顺序分层，类似的节点类似于表示发生故障的序列的故障节点; 生成由从所述结构的起始节点开始到检测到的类似节点的路径上的一组节点所表示的序列串; 并输出所生成的序列串。

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