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1. 发明授权

US6086626A Method for verification of combinational circuits using a filtering oriented approach 失效
标题翻译：使用基于过滤的方法验证组合电路的方法
公开(公告)号：US6086626A
公开(公告)日：2000-07-11
申请号：US857916
申请日：1997-05-16
申请人： Jawahar Jain , Rajarshi Mukherjee , Koichiro Takayama
发明人： Jawahar Jain , Rajarshi Mukherjee , Koichiro Takayama
IPC分类号： G01R31/28 , G01R31/3183 , G06F17/50 , G06F19/00 , G06Q50/00 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G01R31/318357 , G01R31/318371 , G01R31/318385 , G06F17/504
摘要： A set of filters are arranged in sequence for verification and analysis of digital circuit designs. The filters are either active filters, which are directly involved in verification of circuit designs (e.g., a Binary Decision Diagram (BDD)-based verifier or an automatic test pattern generation (ATPG)-based verifier), or passive filters, which gather information about the circuit or transform the circuit structure in order to simplify the verification problem (e.g., random pattern simulation or circuit partitioning). Given a pair of circuits to be verified, the filter approach first subjects the circuits to very simple, fast techniques having very low memory usage requirements. These steps are followed by a series of increasingly powerful methods that are more time consuming and often require more computer memory for their operation. In between the simpler active filters and the more sophisticated active filters, information about potential equivalent nodes in the circuits is collected and a decision is made as to whether to partition the circuits. The verification methodology is structured such that circuit designs that are easier to verify are never unnecessarily subjected to more expensive techniques. The method provides for a gradual increase in the sophistication of verification techniques applied, according to the difficulty of the verification problem.
摘要翻译：一组滤波器按顺序排列，用于数字电路设计的验证和分析。该过滤器是任一有源滤波器，它直接参与在电路设计中的验证（例如，二元决策图（BDD）系验证或自动测试模式产生（ATPG）系检验器），或无源滤波器，其中收集信息关于电路或转换电路结构，以简化验证问题（例如，随机模式仿真或电路划分）。给定要验证的一对电路，滤波器方法首先使电路以非常简单，快速的技术使用，具有非常低的存储器使用要求。这些步骤之后是一系列日益强大的方法，这些方法更耗时，并且通常需要更多的计算机内存来进行操作。在更简单的有源滤波器和更复杂的有源滤波器之间，收集关于电路中的潜在等效节点的信息，并且决定是否划分电路。验证方法被构造成使得更容易验证的电路设计不会不必要地经受更昂贵的技术。该方法根据验证问题的难度逐渐提高了应用验证技术的复杂性。

2. 发明授权

US06301687B1 Method for verification of combinational circuits using a filtering oriented approach 有权
标题翻译：使用基于过滤的方法验证组合电路的方法
公开(公告)号：US06301687B1
公开(公告)日：2001-10-09
申请号：US09556038
申请日：2000-04-20
申请人： Jawahar Jain , Rajarshi Mukherjee , Koichiro Takayama
发明人： Jawahar Jain , Rajarshi Mukherjee , Koichiro Takayama
IPC分类号： G06F1750
CPC分类号： G01R31/318357 , G01R31/318371 , G01R31/318385 , G06F17/504
摘要： A set of filters are arranged in sequence for verification and analysis of digital circuit designs. The filters are either active filters, which are directly involved in verification of circuit designs (e.g., a Binary Decision Diagram (BDD)-based verifier or an automatic test pattern generation (ATPG)-based verifier), or passive filters, which gather information about the circuit or transform the circuit structure in order to simplify the verification problem (e.g., random pattern simulation or circuit partitioning). Given a pair of circuits to be verified, the filter approach first subjects the circuits to very simple, fast techniques having very low memory usage requirements. These steps are followed by a series of increasingly powerful methods that are more time consuming and often require more computer memory for their operation. In between the simpler active filters and the more sophisticated active filters, information about potential equivalent nodes in the circuits is collected and a decision is made as to whether to partition the circuits. The verification methodology is structured such that circuit designs that are easier to verify are never unnecessarily subjected to more expensive techniques. The method provides for a gradual increase in the sophistication of verification techniques applied, according to the difficulty of the verification problem.
摘要翻译：一组滤波器按顺序排列，用于数字电路设计的验证和分析。滤波器是有源滤波器，其直接涉及电路设计的验证（例如，基于二进制决策图（BDD）的验证器或基于自动测试模式生成（ATPG）的验证器）或无源滤波器，其收集信息关于电路或转换电路结构，以简化验证问题（例如，随机模式仿真或电路划分）。给定要验证的一对电路，滤波器方法首先使电路以非常简单，快速的技术使用，具有非常低的存储器使用要求。这些步骤之后是一系列日益强大的方法，这些方法更耗时，并且通常需要更多的计算机内存来进行操作。在更简单的有源滤波器和更复杂的有源滤波器之间，收集关于电路中的潜在等效节点的信息，并且决定是否划分电路。验证方法被构造成使得更容易验证的电路设计不会不必要地经受更昂贵的技术。该方法根据验证问题的难度逐渐提高了应用验证技术的复杂性。

3. 发明授权

US5649165A Topology-based computer-aided design system for digital circuits and method thereof 失效
标题翻译：用于数字电路的拓扑计算机辅助设计系统及其方法
公开(公告)号：US5649165A
公开(公告)日：1997-07-15
申请号：US399707
申请日：1995-03-03
申请人： Jawahar Jain , Rajarshi Mukherjee
发明人： Jawahar Jain , Rajarshi Mukherjee
IPC分类号： G06F17/50 , H01L21/82 , G06F9/455
CPC分类号： G06F17/5045 , G06F17/504
摘要： A computer-aided design system and method thereof for performing logic design analysis for determining logical interdependencies between points in a digital circuit topology. Such a topology comprises a set of primary outputs and a set of primary inputs, both interconnected with logic gates. The logic gates are interconnected by wires. Each such point comprises a location on a wire carrying a signal asserted into or from one of the logic gates. A representation of such topology is stored in a storage device in the computer-aided design system. A cutset in the topology is selected comprising the logic gates falling in a fan-in of the logic gates leading to a target one of the logic gates. A decision diagram is built for logic gates in the cutset leading from the target logic gate. The logic gates in a potential learning area in the topology are marked. Justification vectors are extracted from the decision diagram for a predetermined Boolean value of the target logic gate. Such logical interdependencies are determined and a representation of the logical interdependencies is stored in a storage device in the computer-aided design system. Boolean operations are performed between the decision diagram and a plurality of other decision diagrams for the logic gates in the potential learning area.
摘要翻译：一种用于执行用于确定数字电路拓扑中的点之间的逻辑相互依赖性的逻辑设计分析的计算机辅助设计系统及其方法。这样的拓扑包括一组初级输出和一组主要输入，两者都与逻辑门互连。逻辑门通过电线互连。每个这样的点包括在线上的位置，其承载断言成逻辑门中的一个逻辑门的信号。这种拓扑的表示存储在计算机辅助设计系统中的存储设备中。选择拓扑中的切片，其包括落入通向逻辑门中的目标逻辑门的逻辑门的扇形的逻辑门。为从目标逻辑门引出的切片中的逻辑门构建了一个决策图。拓扑中的潜在学习区域中的逻辑门被标记。对于目标逻辑门的预定布尔值，从判定图中提取对齐矢量。确定这种逻辑相互依赖性，并且将逻辑相互依赖性的表示存储在计算机辅助设计系统中的存储设备中。在决策图和潜在学习区域中的逻辑门的多个其他决策图之间执行布尔运算。

4. 发明授权

US06532440B1 Multiple error and fault diagnosis based on Xlists 有权
标题翻译：基于Xlists的多重错误和故障诊断
公开(公告)号：US06532440B1
公开(公告)日：2003-03-11
申请号：US09173962
申请日：1998-10-16
申请人： Vamsi Boppana , Rajarshi Mukherjee , Jawahar Jain , Masahiro Fujita
发明人： Vamsi Boppana , Rajarshi Mukherjee , Jawahar Jain , Masahiro Fujita
IPC分类号： G06F1750
CPC分类号： G01R31/31835
摘要： A method and system for locating possible error or fault sites in a circuit or system. A set of nodes are chosen, using error models in some embodiments. By applying X values to the set of nodes in conjunction with three valued logic simulation output responses between the circuit and the specification are determined. Based on the comparison of the output responses between the circuit and the specification, an error probability can be assigned to the set of nodes. A ranked set of nodes is thereby produced with the highest ranked set of nodes being the most likely error or fault site. Furthermore, by determining the relationship of the inputs to the set of nodes to the outputs of the set of nodes in conjunction with test vectors and output responses determined in the specification, an error probability can also be assigned to the set of nodes. Use of symbolic logic variables can assist in determining the relationship of the inputs to the set of nodes to the outputs of the set of nodes.
摘要翻译：一种用于定位电路或系统中可能的错误或故障位置的方法和系统。在一些实施例中使用误差模型来选择一组节点。通过将X值应用于节点集合并结合电路与规范之间的三值逻辑模拟输出响应。基于电路和规范之间的输出响应的比较，可以将错误概率分配给该组节点。由此产生排列的节点集合，其中最高排名的节点集合是最可能的错误或故障站点。此外，通过结合测试来确定输入与节点集合到节点集合的输出的关系在规范中确定的向量和输出响应，也可以将错误概率分配给该组节点。使用符号逻辑变量可以帮助确定输入与节点集合到该组节点的输出的关系。

5. 发明授权

US07032192B2 Performing latch mapping of sequential circuits 有权
标题翻译：执行顺序电路的锁存映射
公开(公告)号：US07032192B2
公开(公告)日：2006-04-18
申请号：US10444232
申请日：2003-05-22
申请人： Mukul R. Prasad , Rajarshi Mukherjee , Jawahar Jain , Kelvin K. C. Ng
发明人： Mukul R. Prasad , Rajarshi Mukherjee , Jawahar Jain , Kelvin K. C. Ng
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： Performing latch mapping includes receiving an initial circuit model representing a first circuit and a second circuit and generating an initial latch mapping for the initial circuit model. The following is repeated until a next latch mapping is at least similar to a current latch mapping to yield a final latch mapping. A current circuit model is constructed according to a previous circuit model. Current potentially equivalent node sets associated with the current circuit model are established in accordance with previous potentially equivalent node sets, where each potentially equivalent node set includes potentially equivalent nodes. Equivalence of the current potentially equivalent node sets is validated, and a current latch mapping is verified in accordance with the validated current potentially equivalent node sets to generate a next latch mapping. The final latch mapping is reported.
摘要翻译：执行锁存映射包括接收表示第一电路和第二电路的初始电路模型，并为初始电路模型生成初始锁存器映射。重复以下操作，直到下一个锁存器映射至少类似于当前锁存器映射以产生最终的锁存器映射。根据先前的电路模型构建电流电路模型。根据先前的潜在等效的节点集建立与当前电路模型相关联的当前潜在等价的节点集，其中每个潜在的等效节点集包括潜在的等效节点。验证当前潜在等效的节点集的等效性，并且根据经验证的当前潜在的等效节点集来验证当前的锁存映射以生成下一个锁存映射。报告最后的锁存映射。

6. 发明授权

US06408424B1 Verification of sequential circuits with same state encoding 有权
标题翻译：具有相同状态编码的时序电路的验证
公开(公告)号：US06408424B1
公开(公告)日：2002-06-18
申请号：US09325886
申请日：1999-06-04
申请人： Rajarshi Mukherjee , Jawahar Jain , Vamsi Boppana
发明人： Rajarshi Mukherjee , Jawahar Jain , Vamsi Boppana
IPC分类号： G06F1750
CPC分类号： G01R31/318357 , G01R31/318371 , G01R31/318392 , G06F17/5022 , G06F17/504
摘要： A system and method for verifying sequential circuits. A single pair of storage elements is selected from a single sequential circuit using the selected pairs of storage elements. A distinguishing sequence of test vectors is computed. Using the computed distinguishing sequence of test vectors, the other storage elements of the sequential circuits are distinguished. Based on the storage elements distinguished in the circuits, a correspondence between the storage elements of the circuits is determined and thus, equivalences between the circuits is found using combinational equivalence checking and the sequential circuit is verified. Alternatively, by using Boolean decision diagrams, the storage elements in the sequential circuit are distinguished and likewise distinguishing groups of storage elements are created. These distinguishing groups are further refined by building new Boolean decision diagrams until no new groupings are created and correspondence between the storage elements of the circuits is determined.
摘要翻译：一种用于验证时序电路的系统和方法。使用所选择的一对存储元件从单个时序电路中选择一对存储元件。计算测试向量的区别序列。使用计算的测试向量的区分序列，区分顺序电路的其他存储元件。基于在电路中区分的存储元件，确定电路的存储元件之间的对应关系，因此，使用组合等价性检查找出电路之间的等效性，并且验证顺序电路。或者，通过使用布尔判定图，区分顺序电路中的存储元件，并且同时区分存储元件组。通过构建新的布尔决策图来进一步改进这些区别组，直到不创建新的分组并且确定电路的存储元件之间的对应关系。

7. 发明授权

US07194710B2 Scheduling events in a boolean satisfiability (SAT) solver 失效
标题翻译：在布尔可满足性（SAT）求解器中调度事件
公开(公告)号：US07194710B2
公开(公告)日：2007-03-20
申请号：US10807959
申请日：2004-03-23
申请人： Mukul R. Prasad , Rajarshi Mukherjee
发明人： Mukul R. Prasad , Rajarshi Mukherjee
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： In one embodiment, a method for scheduling events in a Boolean satisfiability (SAT) solver includes collecting one or more first-order statistics on a search for a valid solution to an SAT problem, deriving one or more second-order statistics on the search from the one or more first-order statistics, and scheduling events in the search according to one or more of the second-order statistics.
摘要翻译：在一个实施例中，一种用于在布尔可满足度（SAT）求解器中调度事件的方法包括在搜索针对SAT问题的有效解决方案时收集一个或多个一阶统计信息，从而导出关于搜索的一个或多个二阶统计信息一个或多个一阶统计信息，以及根据一个或多个二阶统计量的搜索中的调度事件。

8. 发明申请

US20050216871A1 Scheduling events in a boolean satisfiability (SAT) solver 失效
标题翻译：在布尔可满足性（SAT）求解器中调度事件
公开(公告)号：US20050216871A1
公开(公告)日：2005-09-29
申请号：US10807959
申请日：2004-03-23
申请人： Mukul Prasad , Rajarshi Mukherjee
发明人： Mukul Prasad , Rajarshi Mukherjee
IPC分类号： G06N5/04 , G06F17/50
CPC分类号： G06F17/504
摘要： In one embodiment, a method for scheduling events in a Boolean satisfiability (SAT) solver includes collecting one or more first-order statistics on a search for a valid solution to an SAT problem, deriving one or more second-order statistics on the search from the one or more first-order statistics, and scheduling events in the search according to one or more of the second-order statistics.
摘要翻译：在一个实施例中，一种用于在布尔可满足度（SAT）求解器中调度事件的方法包括在搜索针对SAT问题的有效解决方案时收集一个或多个一阶统计信息，从而导出关于搜索的一个或多个二阶统计信息一个或多个一阶统计信息，以及根据一个或多个二阶统计量的搜索中的调度事件。

9. 发明授权

US09069699B2 Identifying inconsistent constraints 有权
标题翻译：识别不一致的约束
公开(公告)号：US09069699B2
公开(公告)日：2015-06-30
申请号：US13074940
申请日：2011-03-29
申请人： Dhiraj Goswami , Soe Myint , Ngai Ngai William Hung , Rajarshi Mukherjee
发明人： Dhiraj Goswami , Soe Myint , Ngai Ngai William Hung , Rajarshi Mukherjee
IPC分类号： G06F7/60 , G06F17/10 , G06F17/11 , G06F17/50
CPC分类号： G06F17/11 , G06F17/5018
摘要： Methods and apparatuses are described for identifying inconsistent constraints. During operation, a system can receive a set of constraints, wherein each constraint is defined over one or more random variables from a set of random variables. If an inconsistency or conflict is detected while solving the set of constraints, the system can identify a phase in a series of phases of the constraint solver where the inconsistency was detected. The system can then try to solve different subsets of the set of constraints to identify smaller subsets of the set of constraints that contain the inconsistency. When the system tries to solve a subset of the set of constraints, the system can determine whether or not an inconsistency is detected in the identified phase while solving the subset of the set of constraints. Next, the system can report the smallest subset of inconsistent constraints that was found to a user.
摘要翻译：描述了用于识别不一致约束的方法和装置。在操作期间，系统可以接收一组约束，其中每个约束被从一组随机变量的一个或多个随机变量上定义。如果在解决一组约束的同时检测到不一致或冲突，则系统可以识别在检测到不一致的约束求解器的一系列阶段中的阶段。系统然后可以尝试解决该组约束的不同子集以识别包含不一致性的约束集合的较小子集。当系统尝试解决约束集合的子集时，系统可以确定在确定的相位集合中是否检测到不一致性，同时解决该组约束的子集。接下来，系统可以报告对用户发现的不一致约束的最小子集。

10. 发明申请

US20120253754A1 METHOD AND APPARATUS FOR IDENTIFYING INCONSISTENT CONSTRAINTS 有权
标题翻译：识别不确定性约束的方法和装置
公开(公告)号：US20120253754A1
公开(公告)日：2012-10-04
申请号：US13074940
申请日：2011-03-29
申请人： Dhiraj Goswami , Soe Myint , Ngai Ngai William Hung , Rajarshi Mukherjee
发明人： Dhiraj Goswami , Soe Myint , Ngai Ngai William Hung , Rajarshi Mukherjee
IPC分类号： G06F17/11
CPC分类号： G06F17/11 , G06F17/5018
摘要： Methods and apparatuses are described for identifying inconsistent constraints. During operation, a system can receive a set of constraints, wherein each constraint is defined over one or more random variables from a set of random variables. If an inconsistency or conflict is detected while solving the set of constraints, the system can identify a phase in a series of phases of the constraint solver where the inconsistency was detected. The system can then try to solve different subsets of the set of constraints to identify smaller subsets of the set of constraints that contain the inconsistency. When the system tries to solve a subset of the set of constraints, the system can determine whether or not an inconsistency is detected in the identified phase while solving the subset of the set of constraints. Next, the system can report the smallest subset of inconsistent constraints that was found to a user.
摘要翻译：描述了用于识别不一致约束的方法和装置。在操作期间，系统可以接收一组约束，其中每个约束被从一组随机变量的一个或多个随机变量上定义。如果在解决一组约束的同时检测到不一致或冲突，则系统可以识别在检测到不一致的约束求解器的一系列阶段中的阶段。系统然后可以尝试解决该组约束的不同子集，以识别包含不一致性的约束集合的较小子集。当系统尝试解决约束集合的子集时，系统可以确定在所确定的阶段中是否检测到不一致性，同时解决该组约束的子集。接下来，系统可以报告对用户发现的不一致约束的最小子集。

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