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1. 发明申请

US20110304944A1 APPARATUS AND METHOD FOR ELECTRONIC SYSTEMS RELIABILITY 有权
标题翻译：电子系统可靠性的装置和方法
公开(公告)号：US20110304944A1
公开(公告)日：2011-12-15
申请号：US12797463
申请日：2010-06-09
申请人： Javier A. Salcedo , David Casey , Graham McCorkell
发明人： Javier A. Salcedo , David Casey , Graham McCorkell
IPC分类号： H02H3/22 , H01L23/60
CPC分类号： H01L27/06 , H01L23/60 , H01L27/0251 , H01L2924/0002 , H02H9/046 , H01L2924/00
摘要： Apparatuses and methods for protecting electronic circuits are disclosed. In one embodiment, an apparatus for providing protection from transient signals comprises an integrated circuit, a pad on a surface of the integrated circuit, and a configurable protection circuit within the integrated circuit. The configurable protection circuit is electrically connected to the pad. The configurable protection circuit comprises a plurality of subcircuits arranged in a cascade, and selection of one or more of the plurality of the subcircuits for operation determines at least one of a holding voltage or a trigger voltage of the configurable protection circuit.
摘要翻译：公开了用于保护电子电路的装置和方法。在一个实施例中，用于从瞬态信号提供保护的装置包括集成电路，集成电路的表面上的焊盘以及集成电路内的可配置保护电路。可配置的保护电路电连接到焊盘。可配置保护电路包括以级联布置的多个子电路，并且用于操作的多个子电路中的一个或多个的选择确定可配置保护电路的保持电压或触发电压中的至少一个。

2. 发明申请

US20110303947A1 APPARATUS AND METHOD FOR PROTECTING ELECTRONIC CIRCUITS 有权
标题翻译：用于保护电子电路的装置和方法
公开(公告)号：US20110303947A1
公开(公告)日：2011-12-15
申请号：US12797461
申请日：2010-06-09
申请人： Javier A. Salcedo , David Casey , Graham McCorkell
发明人： Javier A. Salcedo , David Casey , Graham McCorkell
IPC分类号： H01L27/06 , H01L21/33
CPC分类号： H01L27/0259
摘要： Apparatuses and methods for electronic circuit protection are disclosed. In one embodiment, an apparatus comprises a well having an emitter and a collector region. The well has a doping of a first type, and the emitter and collector regions have a doping of a second type. The emitter region, well, and collector region are configured to operate as an emitter, base, and collector for a first transistor, respectively. The collector region is spaced away from the emitter region to define a spacing. A first spacer and a second spacer are positioned adjacent the well between the emitter and the collector. A conductive plate is positioned adjacent the well and between the first spacer and the second spacer, and a doping adjacent the first spacer, the second spacer, and the plate consists essentially of the first type.
摘要翻译：公开了用于电子电路保护的装置和方法。在一个实施例中，装置包括具有发射极和集电极区的阱。阱具有第一类型的掺杂，并且发射极和集电极区域具有第二类型的掺杂。发射极区域，阱极和集电极区域分别被配置为用作第一晶体管的发射极，基极和集电极。集电极区域与发射极区域间隔开以限定间隔。第一间隔件和第二间隔件位于发射器和收集器之间的阱附近。导电板定位成邻近阱并且位于第一间隔件和第二间隔件之间，并且与第一间隔件相邻的掺杂，第二间隔件和板基本上由第一类型组成。

3. 发明授权

US08829570B2 Switching device for heterojunction integrated circuits and methods of forming the same 有权
标题翻译：用于异质结集成电路的开关装置及其形成方法
公开(公告)号：US08829570B2
公开(公告)日：2014-09-09
申请号：US13416152
申请日：2012-03-09
申请人： Srivatsan Parthasarathy , Javier A. Salcedo , Shuyun Zhang
发明人： Srivatsan Parthasarathy , Javier A. Salcedo , Shuyun Zhang
IPC分类号： H01L33/00
CPC分类号： H01L27/0262
摘要： A switching device for heterojunction integrated circuits is disclosed. According to one aspect, the switching device is configured to protect a circuit from an electro-static discharge (ESD) event. The switching device includes a second base contact region that is configured to be electrically floating, a first base contact region and a collector contact region that are coupled to a first input terminal of the switching device, and an emitter contact region that is coupled to a second input terminal of the switching device. Due in part to capacitive coupling between the first base contact region and the second base contact region, the switching device exhibits a low transient trigger voltage and a fast response to ESD events. Further, the switching device exhibits a high DC trigger voltage (for example, greater than 20V), while maintaining relatively low leakage current during operation (for example, less than about 0.5 μA at 20V DC.
摘要翻译：公开了一种用于异质结集成电路的开关装置。根据一个方面，开关装置被配置为保护电路免受静电放电（ESD）事件的影响。开关器件包括被配置为电浮置的第二基极接触区域，耦合到开关器件的第一输入端子的第一基极接触区域和集电极接触区域以及耦合到开关器件的发射极接触区域第二输入端子。部分地由于第一基极接触区域和第二基极接触区域之间的电容耦合，开关器件表现出低瞬态触发电压和对ESD事件的快速响应。此外，开关器件表现出高直流触发电压（例如，大于20V），同时在操作期间保持较低的漏电流（例如，在20V DC时小于约0.5μA）。

4. 发明申请

US20130320498A1 LOW VOLTAGE PROTECTION DEVICES FOR PRECISION TRANSCEIVERS AND METHODS OF FORMING THE SAME 有权
标题翻译：用于精密收发器的低电压保护装置及其形成方法
公开(公告)号：US20130320498A1
公开(公告)日：2013-12-05
申请号：US13486885
申请日：2012-06-01
申请人： Javier A. Salcedo
发明人： Javier A. Salcedo
IPC分类号： H01L29/73
CPC分类号： H01L29/747 , H01L27/0259 , H01L27/0921
摘要： A bi-directional protection device includes a bi-directional NPN bipolar transistor including an emitter/collector formed from a first n-well region, a base formed from a p-well region, and a collector/emitter formed from a second n-well region. P-type active regions are formed in the first and second n-well regions to form a PNPNP structure, which is isolated from the substrate using dual-tub isolation consisting of an n-type tub and a p-type tub. The dual-tub isolation prevents induced latch-up during integrated circuit powered stress conditions by preventing the wells associated with the PNPNP structure from injecting carriers into the substrate. The size, spacing, and doping concentrations of active regions and wells associated with the PNPNP structure are selected to provide fine-tuned control of the trigger and holding voltage characteristics to enable the bi-directional protection device to be implemented in high voltage applications using low voltage precision interface signaling.
摘要翻译：双向保护装置包括双极NPN双极晶体管，其包括由第一n阱区域形成的发射极/集电极，由p阱区域形成的基极和由第二n阱形成的集电极/发射极地区。在第一和第二n阱区域中形成P型有源区，以形成PNPNP结构，该PNPNP结构使用由n型槽和p型槽构成的双槽隔离与基板隔离。双槽隔离通过防止与PNPNP结构相关联的阱将载流子注入到衬底中来防止在集成电路供电的应力条件期间引起的闩锁。选择与PNPNP结构相关联的有源区和阱的尺寸，间距和掺杂浓度以提供对触发和保持电压特性的微调控制，以使双向保护装置能够在使用低电压的高电压应用中实现电压精密接口信号。

5. 发明申请

US20130032882A1 BI-DIRECTIONAL BLOCKING VOLTAGE PROTECTION DEVICES AND METHODS OF FORMING THE SAME 有权
标题翻译：双向阻塞电压保护装置及其形成方法
公开(公告)号：US20130032882A1
公开(公告)日：2013-02-07
申请号：US13198208
申请日：2011-08-04
申请人： Javier A. Salcedo , Michael Lynch , Brian Moane
发明人： Javier A. Salcedo , Michael Lynch , Brian Moane
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L27/0262 , H01L27/0921
摘要： Bi-directional blocking voltage protection devices and methods of forming the same are disclosed. In one embodiment, a protection device includes an n-well and first and second p-wells disposed on opposite sides of the n-well. The first p-well includes a first P+ region and a first N+ region and the second p-well includes a second P+ region and second N+ region. The device further includes a third P+ region disposed along a boundary of the n-well and the first p-well and a fourth P+ region disposed along a boundary of the n-well and the second p-well. A first gate is disposed between the first N+ region and the third P+ region and a second gate is disposed between the second N+ region and the fourth P+ region. The device provides bi-directional blocking voltage protection during high energy stress events, including in applications operating at very low to medium swing voltages.
摘要翻译：公开了双向阻断电压保护装置及其形成方法。在一个实施例中，保护装置包括n阱以及设置在n阱的相对侧上的第一和第二p阱。第一p阱包括第一P +区和第一N +区，第二p阱包括第二P +区和第二N +区。该装置还包括沿着n阱和第一p阱的边界设置的第三P +区和沿着n阱和第二p阱的边界设置的第四P +区。第一栅极设置在第一N +区域和第三P +区域之间，第二栅极设置在第二N +区域和第四P +区域之间。该器件在高能量应力事件期间提供双向阻断电压保护，包括在非常低至中等摆幅电压下工作的应用。

6. 发明申请

US20120306013A1 METAL OXIDE SEMICONDUCTOR OUTPUT CIRCUITS AND METHODS OF FORMING THE SAME 有权
标题翻译：金属氧化物半导体输出电路及其形成方法
公开(公告)号：US20120306013A1
公开(公告)日：2012-12-06
申请号：US13152867
申请日：2011-06-03
申请人： Colm Donovan , Javier A. Salcedo
发明人： Colm Donovan , Javier A. Salcedo
IPC分类号： H01L29/78 , H01L21/8238 , H01L27/092
CPC分类号： H01L27/0285
摘要： Metal oxide semiconductor (MOS) protection circuits and methods of forming the same are disclosed. In one embodiment, an integrated circuit includes a pad, a p-type MOS (PMOS) transistor, and first and second n-type MOS (NMOS) transistors. The first NMOS transistor includes a drain, a source and a gate electrically connected to the pad, a first supply voltage, and a drain of the PMOS transistor, respectively. The second NMOS transistor includes a gate, a drain, and a source electrically connected to a bias node, a second supply voltage, and a source of the PMOS transistor, respectively. The source of the second NMOS transistor is further electrically connected to a body of the PMOS transistor so as to prevent a current flowing from the drain of the PMOS transistor to the second supply voltage through the body of PMOS transistor when a transient signal event is received on the pad.
摘要翻译：公开了金属氧化物半导体（MOS）保护电路及其形成方法。在一个实施例中，集成电路包括焊盘，p型MOS（PMOS）晶体管以及第一和第二n型MOS（NMOS）晶体管。第一NMOS晶体管分别包括漏极，源极和电连接到焊盘的栅极，PMOS晶体管的第一电源电压和漏极。第二NMOS晶体管分别包括电连接到偏置节点，第二电源电压和PMOS晶体管的源极的栅极，漏极和源极。第二NMOS晶体管的源极进一步电连接到PMOS晶体管的主体，以便当接收到瞬态信号事件时，防止电流从PMOS晶体管的漏极流过PMOS晶体管的主体在垫上。

7. 发明授权

US08637899B2 Method and apparatus for protection and high voltage isolation of low voltage communication interface terminals 有权
标题翻译：低压通信接口端子的保护和高压隔离方法和装置
公开(公告)号：US08637899B2
公开(公告)日：2014-01-28
申请号：US13492677
申请日：2012-06-08
申请人： Javier A. Salcedo
发明人： Javier A. Salcedo
IPC分类号： H01L29/66
CPC分类号： H01L27/0262
摘要： A high voltage isolation protection device for low voltage communication interface systems in mixed-signal high voltage electronic circuit is disclosed. According to one aspect, the protection device includes a semiconductor structure configured to provide isolation between low voltage terminals and protection from transient events. The protection device includes a thyristor having an anode, a cathode, and a gate, and a thyristor cathode-gate control region that is built into the protection device. The protection device is configured to provide multiple built-in path-up to power-high terminals and path-down to power-low terminals at different voltage levels. The protection device also includes independently built-in discharge paths to the common substrate that is connected to a different power-low voltage reference. The conduction paths may be built into a single structure with dual isolation regions. As a result, the protection device enables superior robustness and compact protection solutions for smart power applications.
摘要翻译：公开了一种用于混合信号高压电子电路中的低压通信接口系统的高压隔离保护装置。根据一个方面，保护装置包括被配置为提供低电压端子之间的隔离并且防止瞬态事件的半导体结构。保护装置包括具有阳极，阴极和栅极的晶闸管和内置在保护装置中的晶闸管阴极 - 栅极控制区域。保护装置被配置为在不同的电压电平下向功率上限端子提供多个内置通路，并向下降到低功耗端子。保护装置还包括连接到不同功率低电压基准的独立内置到公共基板的放电路径。传导路径可以内置在具有双隔离区域的单个结构中。因此，保护装置可为智能电源应用提供卓越的鲁棒性和紧凑的保护解决方案。

8. 发明申请

US20130328103A1 METHOD AND APPARATUS FOR PROTECTION AND HIGH VOLTAGE ISOLATION OF LOW VOLTAGE COMMUNICATION INTERFACE TERMINALS 有权
标题翻译：低压通信接口端子的保护和高压隔离方法与装置
公开(公告)号：US20130328103A1
公开(公告)日：2013-12-12
申请号：US13492677
申请日：2012-06-08
申请人： Javier A. Salcedo
发明人： Javier A. Salcedo
IPC分类号： H01L29/747
CPC分类号： H01L27/0262
摘要： A high voltage isolation protection device for low voltage communication interface systems in mixed-signal high voltage electronic circuit is disclosed. According to one aspect, the protection device includes a semiconductor structure configured to provide isolation between low voltage terminals and protection from transient events. The protection device includes a thyristor having an anode, a cathode, and a gate, and a thyristor cathode-gate control region that is built into the protection device. The protection device is configured to provide multiple built-in path-up to power-high terminals and path-down to power-low terminals at different voltage levels. The protection device also includes independently built-in discharge paths to the common substrate that is connected to a different power-low voltage reference. The conduction paths may be built into a single structure with dual isolation regions. As a result, the protection device enables superior robustness and compact protection solutions for smart power applications.
摘要翻译：公开了一种用于混合信号高压电子电路中的低压通信接口系统的高压隔离保护装置。根据一个方面，保护装置包括被配置为提供低电压端子之间的隔离并且防止瞬态事件的半导体结构。保护装置包括具有阳极，阴极和栅极的晶闸管和内置在保护装置中的晶闸管阴极 - 栅极控制区域。保护装置被配置为在不同的电压电平下向功率上限端子提供多个内置通路，并向下降到低功耗端子。保护装置还包括连接到不同功率低电压基准的独立内置到公共基板的放电路径。传导路径可以内置在具有双隔离区域的单个结构中。因此，保护装置可为智能电源应用提供卓越的鲁棒性和紧凑的保护解决方案。

9. 发明授权

US08466489B2 Apparatus and method for transient electrical overstress protection 有权
标题翻译：瞬态电气过载保护装置及方法
公开(公告)号：US08466489B2
公开(公告)日：2013-06-18
申请号：US13021636
申请日：2011-02-04
申请人： Javier A. Salcedo , Karl Sweetland
发明人： Javier A. Salcedo , Karl Sweetland
IPC分类号： H01L29/747 , H01L21/332
CPC分类号： H01L29/747 , H01L27/0262 , H01L29/66386
摘要： An apparatus and method for high voltage transient electrical overstress protection are disclosed. In one embodiment, the apparatus includes an internal circuit electrically connected between a first node and a second node; and a protection circuit electrically connected between the first node and the second node. The protection circuit is configured to protect the internal circuit from transient electrical overstress events while maintaining a relatively high holding voltage upon activation. The holes—or electrons—enhanced conduction protection circuit includes a bi-directional bipolar device having an emitter/collector, a base, and a collector/emitter; a first bipolar transistor having an emitter electrically coupled to the first node, a base electrically coupled to the emitter/collector of the bipolar device, and a collector electrically coupled to the base of the bipolar transistor; and a second bipolar transistor having an emitter electrically coupled to the second node, a base electrically coupled to the collector/emitter of the bipolar device, and a collector electrically coupled to the base of the bipolar transistor.
摘要翻译：公开了一种用于高压瞬态电过载保护的装置和方法。在一个实施例中，该装置包括电连接在第一节点和第二节点之间的内部电路; 以及电连接在第一节点和第二节点之间的保护电路。保护电路被配置为保护内部电路免受瞬态电应力事件的影响，同时在激活时保持相对较高的保持电压。空穴或电子增强的传导保护电路包括具有发射极/集电极，基极和集电极/发射极的双向双极器件; 第一双极晶体管，其具有电耦合到第一节点的发射极，电耦合到双极器件的发射极/集电极的基极，以及电耦合到双极晶体管的基极的集电极; 以及具有电耦合到第二节点的发射极的第二双极晶体管，电耦合到双极器件的集电极/发射极的基极，以及电耦合到双极晶体管的基极的集电极。

10. 发明申请

US20120002337A1 APPARATUS AND METHOD FOR ELECTRONIC CIRCUIT PROTECTION 有权
标题翻译：电子电路保护的装置和方法
公开(公告)号：US20120002337A1
公开(公告)日：2012-01-05
申请号：US12830098
申请日：2010-07-02
申请人： Srivatsan Parthasarathy , Javier A. Salcedo
发明人： Srivatsan Parthasarathy , Javier A. Salcedo
IPC分类号： H02H3/38
CPC分类号： H02H3/22 , H01L27/0259 , H02H9/046
摘要： Apparatuses and methods for providing transient electrical event protection are disclosed. In one embodiment, an apparatus comprises a detection and timing circuit, a current amplification circuit, and a clamping circuit. The detection and timing circuit is configured to detect a presence or absence of a transient electrical event at a first node, and to generate a first current for a first duration upon detection of the transient electrical event. The current amplification circuit is configured to receive the first current from the detection and timing circuit and to amplify the first current to generate a second current. The clamping circuit is electrically connected between the first node and a second node and receives the second current for activation. The clamping circuit is configured to activate a low impedance path between the first and second nodes in response to the second current, and to otherwise deactivate the low impedance path.
摘要翻译：公开了用于提供瞬时电气事件保护的装置和方法。在一个实施例中，一种装置包括检测和定时电路，电流放大电路和钳位电路。检测和定时电路被配置为检测在第一节点处的瞬时电事件的存在或不存在，并且在检测到瞬态电事件时产生第一持续时间的第一电流。电流放大电路被配置为从检测和定时电路接收第一电流并且放大第一电流以产生第二电流。钳位电路电连接在第一节点和第二节点之间，并接收用于激活的第二电流。钳位电路被配置为响应于第二电流来激活第一和第二节点之间的低阻抗路径，并且否则去激活低阻抗路径。

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